Inventor · disambiguated record
Artur Wroblewski
Also filed as: WROBLEWSKI ARTUR
10 granted patents·24 citations·filing 2008–2023
82Inventor score
Top patents by PatentIndex Score
10 records- 0184US9449172B2Memory arrangement and method for detecting an attack on a memory arrangementINFINEON TECHNOLOGIES AG·Filed 2015·Granted Sep 20, 2016·5 cites·19 claims
- 0284US7859421B2Circuit and method for detecting a voltage changeINFINEON TECHNOLOGIES AG·Filed 2009·Granted Dec 28, 2010·13 cites·25 claims
- 0378US9432014B2Circuit arrangement for preventing high current flow during energy-saving modeINFINEON TECHNOLOGIES AG·Filed 2013·Granted Aug 30, 2016·5 cites·15 claims
- 0464US10619311B2Base plate and rail fastening pointVOSSLOH WERKE GMBH·Filed 2014·Granted Apr 14, 2020·1 cites·13 claims
- 0557US12232433B2Semiconductor device and method of forming a semiconductor deviceINFINEON TECHNOLOGIES AG·Filed 2022·Granted Feb 18, 2025·0 cites·19 claims
- 0655US12393739B2Integrated circuit and method for protecting an integrated circuit against reverse engineeringINFINEON TECHNOLOGIES AG·Filed 2022·Granted Aug 19, 2025·0 cites·20 claims
- 0747US12182316B2Integrated circuit protection against reverse engineeringINFINEON TECHNOLOGIES AG·Filed 2023·Granted Dec 31, 2024·0 cites·8 claims
- 0840US7830170B2Logic gateINFINEON TECHNOLOGIES AG·Filed 2008·Granted Nov 9, 2010·0 cites·8 claims
- 0940US7826299B2Method and apparatus for operating maskable memory cellsINFINEON TECHNOLOGIES AG·Filed 2008·Granted Nov 2, 2010·0 cites·9 claims
- 1037US7898836B2Masked memory cellsINFINEON TECHNOLOGIES AG·Filed 2008·Granted Mar 1, 2011·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →