Inventor · disambiguated record
Stanley S. Kulick
Also filed as: KULICK STANLEY S · KULICK STANLEY STEVE
19 granted patents·256 citations·filing 2001–2017
94Inventor score
Top patents by PatentIndex Score
19 records- 0192US7886174B2Memory link trainingINTEL CORP·Filed 2007·Granted Feb 8, 2011·31 cites·11 claims
- 0288US7047374B2Memory read/write reorderingINTEL CORP·Filed 2003·Granted May 16, 2006·87 cites·17 claims
- 0387US9653144B1Apparatuses, methods, and systems for package on package memory refresh and self-refresh rate managementMAN XIUTING C·Filed 2016·Granted May 16, 2017·6 cites·24 claims
- 0487US9285826B2Deterministic clock crossingKULICK STANLEY STEVE·Filed 2011·Granted Mar 15, 2016·17 cites·15 claims
- 0585US6813665B2Interrupt method, system and mediumINTEL CORP·Filed 2001·Granted Nov 2, 2004·57 cites·30 claims
- 0679US7103746B1Method of sparing memory devices containing pinned memoryINTEL CORP·Filed 2003·Granted Sep 5, 2006·27 cites·22 claims
- 0773US8463987B2Scalable schedulers for memory controllersABRAHAM PHILIP·Filed 2008·Granted Jun 11, 2013·5 cites·20 claims
- 0871US7509560B2Mechanism for adjacent-symbol error correction and detectionINTEL CORP·Filed 2003·Granted Mar 24, 2009·16 cites·20 claims
- 0966US8902956B2On-package input/output clustered interface having full and half-duplex modesTHOMAS THOMAS P·Filed 2011·Granted Dec 2, 2014·2 cites·20 claims
- 1063US9143120B2Mechanisms for clock gatingOSBORNE RANDY B·Filed 2011·Granted Sep 22, 2015·2 cites·24 claims
- 1160US9274544B2Sideband initializationKULICK STANLEY STEVE·Filed 2011·Granted Mar 1, 2016·1 cites·24 claims
- 1256US10083735B2Apparatuses, methods, and systems for package on package memory refresh and self-refresh rate managementINTEL CORP·Filed 2017·Granted Sep 25, 2018·0 cites·24 claims
- 1355US9336156B2Method and apparatus for cache line state update in sectored cache with line state trackerZHANG ZHONGYING·Filed 2013·Granted May 10, 2016·1 cites·24 claims
- 1454US8977811B2Scalable schedulers for memory controllersINTEL CORP·Filed 2013·Granted Mar 10, 2015·0 cites·20 claims
- 1552US6832268B2Mechanism to guarantee forward progress for incoming coherent input/output (I/O) transactions for caching I/O agent on address conflict with processor transactionsINTEL CORP·Filed 2002·Granted Dec 14, 2004·4 cites·22 claims
- 1647US9442864B2Bridging circuitry between a memory controller and request agents in a system having multiple system memory protection schemesINTEL CORP·Filed 2013·Granted Sep 13, 2016·0 cites·16 claims
- 1743US7386643B2Mechanism to guarantee forward progress for incoming coherent input/output (I/O) transactions for caching I/O agent on address conflict with processor transactionsTAN SIN S·Filed 2004·Granted Jun 10, 2008·0 cites·20 claims
- 1841US8327222B2Mechanism for adjacent-symbol error correction and detectionALEXANDER JAMES W·Filed 2009·Granted Dec 4, 2012·0 cites·20 claims
- 1936US10025732B2Preserving deterministic early valid across a clock domain crossingINTEL CORP·Filed 2016·Granted Jul 17, 2018·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →