Inventor · disambiguated record
Theodore W. Houston
Also filed as: HOUSTON THEODORE · HOUSTON THEODORE W · HOUSTON THEODORE WARREN
249 granted patents·29 pending applications·6,443 citations·filing 1978–2018
99Inventor score
Files withTEXAS INSTRUMENTS INC218HOUSTON THEODORE W35SESHADRI ANAND3DENG XIAOWEI2TEXAS INSTURMENTS INC2
Top patents by PatentIndex Score
278 records- 0198US7400523B28T SRAM cell with higher voltage on the read WLTEXAS INSTRUMENTS INC·Filed 2006·Granted Jul 15, 2008·63 cites·19 claims
- 0298US6954918B2Integrated circuit cellsTEXAS INSTRUMENTS INC·Filed 2003·Granted Oct 11, 2005·223 cites·7 claims
- 0398US6737347B1Semiconductor device with fully self-aligned local interconnects, and method for fabricating the deviceTEXAS INSTRUMENTS INC·Filed 2000·Granted May 18, 2004·214 cites·7 claims
- 0498US6703673B2SOI DRAM having P-doped poly gate for a memory pass transistorTEXAS INSTRUMENTS INC·Filed 2002·Granted Mar 9, 2004·142 cites·13 claims
- 0598US6424016B1SOI DRAM having P-doped polysilicon gate for a memory pass transistorTEXAS INSTRUMENTS INC·Filed 1997·Granted Jul 23, 2002·216 cites·23 claims
- 0698US6177300B1Memory with storage cells having SOI drive and access transistors with tied floating body connectionsTEXAS INSTRUMENTS INC·Filed 1999·Granted Jan 23, 2001·211 cites·30 claims
- 0797US7164596B1SRAM cell with column select lineTEXAS INSTRUMENTS INC·Filed 2005·Granted Jan 16, 2007·72 cites·26 claims
- 0897US5943258AMemory with storage cells having SOI drive and access transistors with tied floating body connectionsTEXAS INSTRUMENTS INC·Filed 1997·Granted Aug 24, 1999·173 cites·28 claims
- 0997US5615162ASelective power to memoryTEXAS INSTRUMENTS INC·Filed 1995·Granted Mar 25, 1997·191 cites·26 claims
- 1096US7816740B2Memory cell layout structure with outer bitlineTEXAS INSTRUMENTS INC·Filed 2008·Granted Oct 19, 2010·38 cites·20 claims
- 1196US7742326B28T SRAM cell with higher voltage on the read WLTEXAS INSTRUMENTS INC·Filed 2008·Granted Jun 22, 2010·33 cites·7 claims
- 1295US7327591B2Staggered memory cell arrayTEXAS INSTRUMENTS INC·Filed 2004·Granted Feb 5, 2008·109 cites·27 claims
- 1395US7236396B2Area efficient implementation of small blocks in an SRAM arrayTEXAS INSTRUMENTS INC·Filed 2005·Granted Jun 26, 2007·58 cites·30 claims
- 1495US6925025B2SRAM device and a method of powering-down the sameTEXAS INSTRUMENTS INC·Filed 2003·Granted Aug 2, 2005·94 cites·20 claims
- 1595US6787469B2Double pattern and etch of poly with hard maskTEXAS INSTRUMENTS INC·Filed 2002·Granted Sep 7, 2004·99 cites·23 claims
- 1695US5396110APulse generator circuit and methodTEXAS INSTRUMENTS INC·Filed 1993·Granted Mar 7, 1995·94 cites·13 claims
- 1794US9236113B2Read assist for an SRAM using a word line suppression circuitTEXAS INSTRUMENTS INC·Filed 2014·Granted Jan 12, 2016·17 cites·3 claims
- 1894US7983071B2Dual node access storage cell having buffer circuitsTEXAS INSTRUMENTS INC·Filed 2008·Granted Jul 19, 2011·24 cites·18 claims
- 1994US7289354B2Memory array with a delayed wordline boostTEXAS INSTRUMENTS INC·Filed 2005·Granted Oct 30, 2007·26 cites·11 claims
- 2093US7710763B2SRAM cell using separate read and write circuitryTEXAS INSTRUMENTS INC·Filed 2008·Granted May 4, 2010·24 cites·17 claims
- 2193US5185280AMethod of fabricating a soi transistor with pocket implant and body-to-source (bts) contactTEXAS INSTRUMENTS INC·Filed 1991·Granted Feb 9, 1993·117 cites·2 claims
- 2293US5018102AMemory having selected state on power-upTEXAS INSTRUMENTS INC·Filed 1988·Granted May 21, 1991·75 cites·9 claims
- 2392US7483332B2SRAM cell using separate read and write circuitryTEXAS INSTRUMENTS INC·Filed 2005·Granted Jan 27, 2009·25 cites·9 claims
- 2492US6611451B1Memory array and wordline driver supply voltage differential in standbyTEXAS INSTRUMENTS INC·Filed 2002·Granted Aug 26, 2003·62 cites·12 claims
- 2592US6461933B2SPIMOX/SIMOX combination with ITOX optionTEXAS INSTRUMENTS INC·Filed 2001·Granted Oct 8, 2002·71 cites·5 claims
- 2692US6061267AMemory circuits, systems, and methods with cells using back bias to control the threshold voltage of one or more corresponding cell transistorsTEXAS INSTRUMENTS INC·Filed 1998·Granted May 9, 2000·96 cites·11 claims
- 2791US9082507B2Read assist circuit for an SRAM, including a word line suppression circuitTEXAS INSTRUMENTS INC·Filed 2014·Granted Jul 14, 2015·11 cites·7 claims
- 2891US7564725B2SRAM bias for read and writeTEXAS INSTRUMENTS INC·Filed 2007·Granted Jul 21, 2009·26 cites·31 claims
- 2991US7307907B2SRAM device and a method of operating the same to reduce leakage current during a sleep modeTEXAS INSTRUMENTS INC·Filed 2003·Granted Dec 11, 2007·61 cites·29 claims
- 3091US6768144B2Method and apparatus for reducing leakage current in an SRAM arrayTEXAS INSTRUMENTS INC·Filed 2001·Granted Jul 27, 2004·46 cites·36 claims
- 3191US6573549B1Dynamic threshold voltage 6T SRAM cellTEXAS INSTRUMENTS INC·Filed 2002·Granted Jun 3, 2003·64 cites·7 claims
- 3291US5214610AMemory with selective address transition detection for cache operationTEXAS INSTRUMENTS INC·Filed 1991·Granted May 25, 1993·84 cites·12 claims
- 3390US8755239B2Read assist circuit for an SRAMHOLLA LAKSHMIKANTHA V·Filed 2011·Granted Jun 17, 2014·16 cites·9 claims
- 3490US7864600B2Memory cell employing reduced voltageTEXAS INSTRUMENTS INC·Filed 2008·Granted Jan 4, 2011·18 cites·14 claims
- 3590US7745867B2Integrated DRAM process/structure using contact pillarsTEXAS INSTRUMENTS INC·Filed 2008·Granted Jun 29, 2010·12 cites·2 claims
- 3690US7027346B2Bit line control for low power in standbyTEXAS INSTRUMENTS INC·Filed 2003·Granted Apr 11, 2006·46 cites·19 claims
- 3790US5461577AComprehensive logic circuit layout systemTEXAS INSTRUMENTS INC·Filed 1992·Granted Oct 24, 1995·134 cites·21 claims
- 3889US8379433B23T DRAM cell with added capacitance on storage nodeTEXAS INSTRUMENTS INC·Filed 2010·Granted Feb 19, 2013·20 cites·17 claims
- 3989US8248867B2Memory cell employing reduced voltageMIKAN JR DONALD GEORGE·Filed 2010·Granted Aug 21, 2012·14 cites·7 claims
- 4089US8174058B2Integrated circuits with split gate and common gate FinFET transistorsMARSHALL ANDREW·Filed 2011·Granted May 8, 2012·10 cites·13 claims
- 4189US7888192B2Process for forming integrated circuits with both split gate and common gate FinFET transistorsTEXAS INSTRUMENTS INC·Filed 2008·Granted Feb 15, 2011·14 cites·18 claims
- 4289US7512030B2Memory with low power mode for WRITETEXAS INSTRUMENTS INC·Filed 2006·Granted Mar 31, 2009·19 cites·18 claims
- 4389US5917365AOptimizing the operating characteristics of a CMOS integrated circuitTEXAS INSTRUMENTS INC·Filed 1997·Granted Jun 29, 1999·62 cites·20 claims
- 4489US5208489AMultiple compound domino logic circuitTEXAS INSTRUMENTS INC·Filed 1990·Granted May 4, 1993·57 cites·27 claims
- 4588US8310860B1SRAM strap row double well contactHOUSTON THEODORE W·Filed 2011·Granted Nov 13, 2012·10 cites·9 claims
- 4688US7936623B2Universal structure for memory cell characterizationTEXAS INSTRUMENTS INC·Filed 2007·Granted May 3, 2011·11 cites·27 claims
- 4787US8437214B2Memory cell employing reduced voltageMIKAN DONALD·Filed 2012·Granted May 7, 2013·11 cites·2 claims
- 4887US7570527B2Static random-access memory having reduced bit line precharge voltage and method of operating the sameTEXAS INSTRUMENTS INC·Filed 2005·Granted Aug 4, 2009·19 cites·22 claims
- 4987US6045625ABuried oxide with a thermal expansion matching layer for SOITEXAS INSTRUMENTS INC·Filed 1997·Granted Apr 4, 2000·85 cites·15 claims
- 5087US5905290ASingle event upset hardened memory cellTEXAS INSTRUMENTS INC·Filed 1993·Granted May 18, 1999·61 cites·32 claims
Showing the top 50 of 278 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →