Inventor · disambiguated record
Yannick Feurprier
Also filed as: FEURPRIER YANNICK
16 granted patents·1 pending application·101 citations·filing 2006–2021
92Inventor score
Top patents by PatentIndex Score
17 records- 0196US9373582B1Self aligned via in integrated circuitIBM·Filed 2015·Granted Jun 21, 2016·18 cites·8 claims
- 0294US9385078B1Self aligned via in integrated circuitIBM·Filed 2016·Granted Jul 5, 2016·11 cites·1 claims
- 0391US8809185B1Dry etching method for metallization pattern profilingTOKYO ELECTRON LTD·Filed 2013·Granted Aug 19, 2014·14 cites·17 claims
- 0487US9607834B2Trench and hole patterning with EUV resists using dual frequency capacitively coupled plasma (CCP)TOKYO ELECTRON LTD·Filed 2016·Granted Mar 28, 2017·5 cites·20 claims
- 0587US7637269B1Low damage method for ashing a substrate using CO2/CO-based processTOKYO ELECTRON LTD·Filed 2009·Granted Dec 29, 2009·17 cites·19 claims
- 0686US9818610B2Trench and hole patterning with EUV resists using dual frequency capacitively coupled plasma (CCP)TOKYO ELECTRON LTD·Filed 2017·Granted Nov 14, 2017·4 cites·7 claims
- 0785US7723237B2Method for selective removal of damaged multi-stack bilayer filmsTOKYO ELECTRON LTD·Filed 2006·Granted May 25, 2010·12 cites·21 claims
- 0878US8202803B2Method to remove capping layer of insulation dielectric in interconnect structuresFEURPRIER YANNICK·Filed 2009·Granted Jun 19, 2012·7 cites·16 claims
- 0974US7947609B2Method for etching low-k material using an oxide hard maskTOKYO ELECTRON LTD·Filed 2007·Granted May 24, 2011·6 cites·9 claims
- 1072US7935640B2Method for forming a damascene structureTOKYO ELECTRON LTD·Filed 2007·Granted May 3, 2011·4 cites·14 claims
- 1167US9768113B2Self aligned via in integrated circuitIBM·Filed 2016·Granted Sep 19, 2017·1 cites·11 claims
- 1263US11495490B2Semiconductor device manufacturing methodTOKYO ELECTRON LTD·Filed 2020·Granted Nov 8, 2022·0 cites·5 claims
- 1358US8080473B2Method for metallizing a pattern in a dielectric filmFEURPRIER YANNICK·Filed 2007·Granted Dec 20, 2011·2 cites·14 claims
- 1455US10910259B2Semiconductor device manufacturing methodTOKYO ELECTRON LTD·Filed 2018·Granted Feb 2, 2021·0 cites·8 claims
- 1550US12438038B2Forming vias in a semiconductor deviceTOKYO ELECTRON LTD·Filed 2021·Granted Oct 7, 2025·0 cites·20 claims
- 1643US11087973B2Method of selective deposition for BEOL dielectric etchTOKYO ELECTRON LTD·Filed 2017·Granted Aug 10, 2021·0 cites·21 claims
- 1743US2015076707A1Integrated circuit via structure and method of fabricationST MICROELECTRONICS INC·Filed 2013·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →