Inventor · disambiguated record
Vaishali Kulkarni
Also filed as: KULKARNI VAISHALI · KULKARNI VAISHALI SHASHANK
12 granted patents·3 pending applications·44 citations·filing 1999–2024
86Inventor score
Top patents by PatentIndex Score
15 records- 0189US11698869B1Computing an authentication tag for partial transfers scheduled across multiple direct memory access (DMA) enginesNVIDIA CORP·Filed 2022·Granted Jul 11, 2023·3 cites·20 claims
- 0278US9880603B1Methods and apparatus for clock gating processing modules based on hierarchy and workloadJUNIPER NETWORKS INC·Filed 2013·Granted Jan 30, 2018·4 cites·21 claims
- 0377US11720440B2Error containment for enabling local checkpoint and recoveryNVIDIA CORP·Filed 2021·Granted Aug 8, 2023·1 cites·19 claims
- 0469US10474665B2Systems and methods for generating blueprints for enterprisesTATA CONSULTANCY SERVICES LTD·Filed 2016·Granted Nov 12, 2019·1 cites·17 claims
- 0567US10229416B2Issue extraction based on ticket miningTATA CONSULTANCY SERVICES LTD·Filed 2015·Granted Mar 12, 2019·1 cites·12 claims
- 0666US12499080B2Method and apparatus for supporting distributed graphics and compute engines and synchronization in multi-dielet parallel processor architecturesNVIDIA CORP·Filed 2024·Granted Dec 16, 2025·0 cites·20 claims
- 0759US9477257B1Methods and apparatus for limiting a number of current changes while clock gating to manage power consumption of processor modulesJUNIPER NETWORKS INC·Filed 2013·Granted Oct 25, 2016·1 cites·17 claims
- 0858US6553502B1Graphics user interface for power optimization diagnosticsTEXAS INSTRUMENTS INC·Filed 1999·Granted Apr 22, 2003·33 cites·25 claims
- 0955US10571988B1Methods and apparatus for clock gating processing modules based on hierarchy and workloadJUNIPER NETWORKS INC·Filed 2018·Granted Feb 25, 2020·0 cites·20 claims
- 1053US12001592B2Protecting against resets by untrusted software during cryptographic operationsNVIDIA CORP·Filed 2022·Granted Jun 4, 2024·0 cites·20 claims
- 1151US2025291591A1Method and apparatus for supporting distributed graphics and compute engines and synchronization in multi-dielet parallel processor architectures -- memory barriersNVIDIA CORP·Filed 2024·Application pending·0 cites
- 1249US11966480B2Fairly utilizing multiple contexts sharing cryptographic hardwareNVIDIA CORP·Filed 2022·Granted Apr 23, 2024·0 cites·20 claims
- 1349US2025272167A1Partition-aware broadcast operation filtering in a multiprocessor systemNVIDIA CORP·Filed 2024·Application pending·0 cites
- 1448US9753524B1Methods and apparatus for limiting a number of current changes while clock gating to manage power consumption of processor modulesJUNIPER NETWORKS INC·Filed 2016·Granted Sep 5, 2017·0 cites·20 claims
- 1548US2025291730A1Hardware assisted Page Migration in a Multi-Dielet Processing SystemNVIDIA CORP·Filed 2024·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →