Inventor · disambiguated record
Enric Gibert Codina
Also filed as: CODINA ENRIC G · CODINA ENRIC GIBERT
9 granted patents·1 pending application·23 citations·filing 2009–2014
82Inventor score
Technology areasG06F
Top patents by PatentIndex Score
10 records- 0177US8909902B2Systems, methods, and apparatuses to decompose a sequential program into multiple threads, execute said threads, and reconstruct the sequential executionLATORRE FERNANDO·Filed 2009·Granted Dec 9, 2014·10 cites·13 claims
- 0270US9329848B2Mechanism for facilitating dynamic and efficient fusion of computing instructions in software programsLUPON MARC·Filed 2013·Granted May 3, 2016·4 cites·20 claims
- 0368US9940138B2Utilization of register checkpointing mechanism with pointer swapping to resolve multithreading mis-speculationsLOPEZ PEDRO·Filed 2009·Granted Apr 10, 2018·5 cites·20 claims
- 0462US10621092B2Merging level cache and data cache units having indicator bits related to speculative executionINTEL CORP·Filed 2014·Granted Apr 14, 2020·1 cites·20 claims
- 0561US9116719B2Partial commits in dynamic binary translation based systemsMARTINEZ RAUL·Filed 2013·Granted Aug 25, 2015·1 cites·25 claims
- 0658US9983880B2Method and apparatus for improved thread selectionINTEL CORP·Filed 2014·Granted May 29, 2018·1 cites·16 claims
- 0753US8898646B2Method and apparatus for flexible, accurate, and/or efficient code profilingCODINA ENRIC GIBERT·Filed 2010·Granted Nov 25, 2014·1 cites·16 claims
- 0848US9389871B2Combined floating point multiplier adder with intermediate rounding logicINTEL CORP·Filed 2013·Granted Jul 12, 2016·0 cites·30 claims
- 0942US10157063B2Instruction and logic for optimization level aware branch predictionINTEL CORP·Filed 2012·Granted Dec 18, 2018·0 cites·6 claims
- 1040US2016011874A1Silent memory instructions and miss-rate tracking to optimize switching policy on threads in a processing deviceORENSTEIN DORON·Filed 2014·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →