Inventor · disambiguated record
Mohammad Abdallah
Also filed as: ABDALLAH MOHAMMAD · ABDALLAH MOHAMMAD A · ABDALLAH MOHAMMAD A F
92 granted patents·1 pending application·2,155 citations·filing 1998–2021
99Inventor score
Top patents by PatentIndex Score
93 records- 0197US6718440B2Memory access latency hiding with hint bufferINTEL CORP·Filed 2001·Granted Apr 6, 2004·211 cites·23 claims
- 0295US6754812B1Hardware predication for conditional instruction path branchingINTEL CORP·Filed 2000·Granted Jun 22, 2004·160 cites·21 claims
- 0393US10198266B2Method for populating register view data structure by using register template snapshotsINTEL CORP·Filed 2017·Granted Feb 5, 2019·9 cites·18 claims
- 0493US6502115B2Conversion between packed floating point data and packed 32-bit integer data in different architectural registersINTEL CORP·Filed 2001·Granted Dec 31, 2002·50 cites·55 claims
- 0593US6377970B1Method and apparatus for computing a sum of packed data elements using SIMD multiply circuitryINTEL CORP·Filed 1998·Granted Apr 23, 2002·173 cites·32 claims
- 0693US6282554B1Method and apparatus for floating point operations and format conversion operationsINTEL CORP·Filed 1998·Granted Aug 28, 2001·97 cites·16 claims
- 0791US10585670B2Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to referINTEL CORP·Filed 2018·Granted Mar 10, 2020·5 cites·14 claims
- 0890US9811342B2Method for performing dual dispatch of blocks and half blocksINTEL CORP·Filed 2014·Granted Nov 7, 2017·11 cites·16 claims
- 0990US7430656B2System and method of converting data formats and communicating between execution unitsINTEL CORP·Filed 2002·Granted Sep 30, 2008·68 cites·10 claims
- 1090US7216138B2Method and apparatus for floating point operations and format conversion operationsINTEL CORP·Filed 2001·Granted May 8, 2007·40 cites·30 claims
- 1188US6115812AMethod and apparatus for efficient vertical SIMD computationsINTEL CORP·Filed 1998·Granted Sep 5, 2000·169 cites·18 claims
- 1288US6041404ADual function system and method for shuffling packed data elementsINTEL CORP·Filed 1998·Granted Mar 21, 2000·162 cites·24 claims
- 1387US6292815B1Data conversion between floating point packed format and integer scalar formatINTEL CORP·Filed 1998·Granted Sep 18, 2001·98 cites·36 claims
- 1486US10417000B2Method for a delayed branch implementation by using a front end track tableINTEL CORP·Filed 2017·Granted Sep 17, 2019·3 cites·17 claims
- 1586US10140138B2Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulationINTEL CORP·Filed 2014·Granted Nov 27, 2018·10 cites·36 claims
- 1686US10083041B2Instruction sequence buffer to enhance branch prediction efficiencyINTEL CORP·Filed 2018·Granted Sep 25, 2018·3 cites·20 claims
- 1786US9842005B2Register file segments for supporting code block execution by using virtual cores instantiated by partitionable enginesABDALLAH MOHAMMAD·Filed 2012·Granted Dec 12, 2017·8 cites·24 claims
- 1886US9678755B2Instruction sequence buffer to enhance branch prediction efficiencyABDALLAH MOHAMMAD·Filed 2011·Granted Jun 13, 2017·7 cites·15 claims
- 1986US6480868B2Conversion from packed floating point data to packed 8-bit integer data in different architectural registersINTEL CORP·Filed 2001·Granted Nov 12, 2002·37 cites·26 claims
- 2085US6918032B1Hardware predication for conditional instruction path branchingINTEL CORP·Filed 2000·Granted Jul 12, 2005·51 cites·13 claims
- 2185US6266769B1Conversion between packed floating point data and packed 32-bit integer data in different architectural registersINTEL CORP·Filed 1998·Granted Jul 24, 2001·49 cites·25 claims
- 2284US7761694B2Execution unit for performing shuffle and other operationsINTEL CORP·Filed 2006·Granted Jul 20, 2010·23 cites·24 claims
- 2380US7467286B2Executing partial-width packed data instructionsINTEL CORP·Filed 2005·Granted Dec 16, 2008·8 cites·29 claims
- 2479US10467010B2Method and apparatus for nearest potential store taggingINTEL CORP·Filed 2014·Granted Nov 5, 2019·5 cites·15 claims
- 2579US10048964B2Disambiguation-free out of order load store queueINTEL CORP·Filed 2014·Granted Aug 14, 2018·4 cites·21 claims
- 2678US10019263B2Reordered speculative instruction sequences with a disambiguation-free out of order load store queueINTEL CORP·Filed 2014·Granted Jul 10, 2018·4 cites·24 claims
- 2778US9921842B2Guest instruction block with near branching and far branching sequence construction to native instruction blockINTEL CORP·Filed 2016·Granted Mar 20, 2018·2 cites·24 claims
- 2878US9817666B2Method for a delayed branch implementation by using a front end track tableINTEL CORP·Filed 2014·Granted Nov 14, 2017·3 cites·15 claims
- 2978US6192467B1Executing partial-width packed data instructionsINTEL CORP·Filed 1998·Granted Feb 20, 2001·82 cites·43 claims
- 3077US9753691B2Method for a stage optimized high speed adderINTEL CORP·Filed 2014·Granted Sep 5, 2017·3 cites·18 claims
- 3176US9928179B2Cache replacement policyAVUDAIYAPPAN KARTHIKEYAN·Filed 2011·Granted Mar 27, 2018·4 cites·17 claims
- 3275US10394563B2Hardware accelerated conversion system using pattern matchingINTEL CORP·Filed 2016·Granted Aug 27, 2019·1 cites·20 claims
- 3375US10248570B2Methods, systems and apparatus for predicting the way of a set associative cacheINTEL CORP·Filed 2018·Granted Apr 2, 2019·1 cites·20 claims
- 3475US7516307B2Processor for computing a packed sum of absolute differences and packed multiply-addINTEL CORP·Filed 2001·Granted Apr 7, 2009·18 cites·12 claims
- 3575US6247116B1Conversion from packed floating point data to packed 16-bit integer data in different architectural registersINTEL CORP·Filed 1998·Granted Jun 12, 2001·69 cites·41 claims
- 3674US6243803B1Method and apparatus for computing a packed absolute differences with plurality of sign bits using SIMD add circuitryINTEL CORP·Filed 1998·Granted Jun 5, 2001·66 cites·22 claims
- 3773US6263426B1Conversion from packed floating point data to packed 8-bit integer data in different architectural registersINTEL CORP·Filed 1998·Granted Jul 17, 2001·55 cites·19 claims
- 3873US6122725AExecuting partial-width packed data instructionsINTEL CORP·Filed 1998·Granted Sep 19, 2000·65 cites·13 claims
- 3972US9928121B2Method and system for implementing recovery from speculative forwarding miss-predictions/errors resulting from load store reordering and optimizationINTEL CORP·Filed 2014·Granted Mar 27, 2018·2 cites·18 claims
- 4070US10031784B2Interconnect system to support the execution of instruction sequences by a plurality of partitionable enginesINTEL CORP·Filed 2016·Granted Jul 24, 2018·1 cites·16 claims
- 4170US9891924B2Method for implementing a reduced size register view data structure in a microprocessorINTEL CORP·Filed 2014·Granted Feb 13, 2018·2 cites·15 claims
- 4270US6970994B2Executing partial-width packed data instructionsINTEL CORP·Filed 2001·Granted Nov 29, 2005·12 cites·117 claims
- 4370US6426746B2Optimization for 3-D graphic transformation using SIMD computationsINTEL CORP·Filed 1998·Granted Jul 30, 2002·45 cites·30 claims
- 4469US11656875B2Method and system for instruction block to execution unit groupingINTEL CORP·Filed 2020·Granted May 23, 2023·0 cites·18 claims
- 4569US11204769B2Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable enginesINTEL CORP·Filed 2020·Granted Dec 21, 2021·0 cites·18 claims
- 4669US7133040B1System and method for performing an insert-extract instructionINTEL CORP·Filed 1998·Granted Nov 7, 2006·56 cites·21 claims
- 4769US6233671B1Staggering execution of an instruction by dividing a full-width macro instruction into at least two partial-width micro instructionsINTEL CORP·Filed 1998·Granted May 15, 2001·63 cites·11 claims
- 4868US6085312AMethod and apparatus for handling imprecise exceptionsINTEL CORP·Filed 1998·Granted Jul 4, 2000·50 cites·28 claims
- 4967US6584549B2System and method for prefetching data into a cache based on miss distanceINTEL CORP·Filed 2000·Granted Jun 24, 2003·10 cites·28 claims
- 5066US11163720B2Apparatus and method for processing an instruction matrix specifying parallel and dependent operationsINTEL CORP·Filed 2019·Granted Nov 2, 2021·0 cites·18 claims
Showing the top 50 of 93 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Mohammad Abdallah files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →