Inventor · disambiguated record
Matthew W. Moskewicz
Also filed as: MOSKEWICZ MATTHEW · MOSKEWICZ MATTHEW W
20 granted patents·364 citations·filing 2002–2013
96Inventor score
Technology areasG06F
Top patents by PatentIndex Score
20 records- 0197US7653892B1System and method for implementing image-based design rulesCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Jan 26, 2010·48 cites·16 claims
- 0297US7418693B1System and method for analysis and transformation of layouts using situationsCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Aug 26, 2008·72 cites·10 claims
- 0396US7818707B1Fast pattern matchingCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Oct 19, 2010·36 cites·25 claims
- 0494US7707542B1Creating a situation repositoryCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Apr 27, 2010·24 cites·27 claims
- 0593US9519732B1Methods, systems, and articles of manufacture for implementing pattern-based design enabled manufacturing of electronic circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Dec 13, 2016·18 cites·23 claims
- 0693US7831942B1Design check databaseCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Nov 9, 2010·20 cites·48 claims
- 0791US9053259B1Methods, systems, and articles of manufacture for implementing pattern-based design enabled manufacturing of electronic circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Jun 9, 2015·16 cites·21 claims
- 0891US8079005B2Method and system for performing pattern classification of patterns in integrated circuit designsLAI YA-CHIEH·Filed 2008·Granted Dec 13, 2011·29 cites·29 claims
- 0990US8769474B1Fast pattern matchingGENNARI FRANK E·Filed 2010·Granted Jul 1, 2014·8 cites·20 claims
- 1090US8327299B1System and method for implementing image-based design rulesGENNARI FRANK E·Filed 2009·Granted Dec 4, 2012·13 cites·20 claims
- 1188US8365103B1System and method for implementing image-based design rulesCADENCE DESIGN SYSTEMS INC·Filed 2009·Granted Jan 29, 2013·10 cites·33 claims
- 1288US7752577B1Constraint plus patternCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Jul 6, 2010·11 cites·51 claims
- 1386US8677301B2Method and system for model-based design and layout of an integrated circuitLAI YA-CHIEH·Filed 2012·Granted Mar 18, 2014·8 cites·20 claims
- 1486US8631373B1Yield analysis with situationsGENNARI FRANK E·Filed 2009·Granted Jan 14, 2014·8 cites·19 claims
- 1583US8645887B2Method and system for model-based design and layout of an integrated circuitLAI YA-CHIEH·Filed 2012·Granted Feb 4, 2014·6 cites·20 claims
- 1683US8381152B2Method and system for model-based design and layout of an integrated circuitCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted Feb 19, 2013·10 cites·33 claims
- 1782US8086981B2Method and system for design rule checking enhanced with pattern matchingLAI YA-CHIEH·Filed 2008·Granted Dec 27, 2011·12 cites·26 claims
- 1878US7661087B1Yield analysis with situationsCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Feb 9, 2010·4 cites·24 claims
- 1976US8091047B1System and method for implementing image-based design rulesGENNARI FRANK E·Filed 2009·Granted Jan 3, 2012·3 cites·20 claims
- 2061US7418369B2Method and system for efficient implementation of boolean satisfiabilityUNIV PRINCETON·Filed 2002·Granted Aug 26, 2008·8 cites·31 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →