Inventor · disambiguated record
Ramesh Peri
Also filed as: PERI RAMESH · PERI RAMESH V
12 granted patents·4 pending applications·281 citations·filing 1997–2021
91Inventor score
Files withINTEL CORP9HEWLETT PACKARD CO2LUCENT TECHNOLOGIES INC2AGERE SYST GUARDIAN CORP1OHLY PATRICK1
Top patents by PatentIndex Score
16 records- 0182US6079032APerformance analysis of computer systemsLUCENT TECHNOLOGIES INC·Filed 1998·Granted Jun 20, 2000·107 cites·14 claims
- 0274US7840845B2Method and system for setting a breakpointINTEL CORP·Filed 2005·Granted Nov 23, 2010·9 cites·2 claims
- 0369US6253373B1Tracking loop entry and exit points in a compilerHEWLETT PACKARD CO·Filed 1997·Granted Jun 26, 2001·57 cites·28 claims
- 0457US7581213B2Allocating automatic variables to different memory banksINTEL CORP·Filed 2004·Granted Aug 25, 2009·6 cites·20 claims
- 0557US6467082B1Methods and apparatus for simulating external linkage points and control transfers in source translation systemsAGERE SYST GUARDIAN CORP·Filed 1998·Granted Oct 15, 2002·39 cites·40 claims
- 0656US7346735B2Virtualized load buffersINTEL CORP·Filed 2004·Granted Mar 18, 2008·4 cites·16 claims
- 0755US12001382B2Methods, apparatus, and articles of manufacture to generate command lists to be offloaded to accelerator circuitryINTEL CORP·Filed 2021·Granted Jun 4, 2024·0 cites·25 claims
- 0853US6088525ALoop profiling by instrumentationHEWLETT PACKARD CO·Filed 1997·Granted Jul 11, 2000·28 cites·46 claims
- 0950US6182208B1System for debugging (N) break points by dividing a computer program to (n+1) regions each contains no break point and using two registers to define the start and end addresses of each regionLUCENT TECHNOLOGIES INC·Filed 1998·Granted Jan 30, 2001·28 cites·10 claims
- 1046US7747992B2Methods and apparatus for creating software basic block layoutsINTEL CORP·Filed 2004·Granted Jun 29, 2010·3 cites·28 claims
- 1146US7533232B2Accessing data from different memory locations in the same cycleINTEL CORP·Filed 2003·Granted May 12, 2009·0 cites·28 claims
- 1245US7577791B2Virtualized load buffersINTEL CORP·Filed 2007·Granted Aug 18, 2009·0 cites·17 claims
- 1345US2005223202A1Branch prediction in a pipelined processorINTEL CORP·Filed 2004·Application pending·0 cites
- 1443US2007168979A1Transparent debugging of programs in dynamic translation systemsINTEL CORP·Filed 2005·Application pending·0 cites
- 1541US2005223364A1Method and apparatus to compact trace in a trace bufferPERI RAMESH V·Filed 2004·Application pending·0 cites
- 1633US2007245171A1Methods and apparatus to perform distributed memory checkingOHLY PATRICK·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →