Inventor · disambiguated record
Khang K. Dao
Also filed as: DAO KHANG K · DAO KHANG KIM
16 granted patents·305 citations·filing 2001–2018
93Inventor score
Files withXILINX INC16
Top patents by PatentIndex Score
16 records- 0196US7266632B2Programmable logic device including programmable interface core and central processing unitXILINX INC·Filed 2006·Granted Sep 4, 2007·61 cites·12 claims
- 0295US7076595B1Programmable logic device including programmable interface core and central processing unitXILINX INC·Filed 2001·Granted Jul 11, 2006·105 cites·45 claims
- 0394US11204747B1Re-targetable interface for data exchange between heterogeneous systems and accelerator abstraction into software instructionsXILINX INC·Filed 2017·Granted Dec 21, 2021·19 cites·20 claims
- 0489US10819680B1Interface firewall for an integrated circuit of an expansion cardXILINX INC·Filed 2018·Granted Oct 27, 2020·9 cites·20 claims
- 0588US7260688B1Method and apparatus for controlling access to memory circuitryXILINX INC·Filed 2004·Granted Aug 21, 2007·56 cites·28 claims
- 0687US11036827B1Software-defined buffer/transposer for general matrix multiplication in a programmable ICXILINX INC·Filed 2017·Granted Jun 15, 2021·7 cites·20 claims
- 0786US10346572B1Inclusion and configuration of a transaction converter circuit block within an integrated circuitXILINX INC·Filed 2017·Granted Jul 9, 2019·5 cites·20 claims
- 0886US7970977B1Deadlock-resistant bus bridge with pipeline-restricted address rangesXILINX INC·Filed 2009·Granted Jun 28, 2011·17 cites·18 claims
- 0984US11474555B1Data-driven platform characteristics capture and discovery for hardware acceleratorsXILINX INC·Filed 2017·Granted Oct 18, 2022·4 cites·20 claims
- 1084US9792395B1Memory utilization in a circuit designXILINX INC·Filed 2016·Granted Oct 17, 2017·5 cites·20 claims
- 1184US7406557B2Programmable logic device including programmable interface core and central processing unitXILINX INC·Filed 2006·Granted Jul 29, 2008·10 cites·18 claims
- 1277US10802995B2Unified address space for multiple hardware accelerators using dedicated low latency linksXILINX INC·Filed 2018·Granted Oct 13, 2020·2 cites·20 claims
- 1368US9183334B1Verification of connectivity of signals in a circuit designXILINX INC·Filed 2014·Granted Nov 10, 2015·2 cites·20 claims
- 1468US8813005B1Debugging using tagged flip-flopsXILINX INC·Filed 2013·Granted Aug 19, 2014·2 cites·19 claims
- 1560US8769449B1System level circuit designXILINX INC·Filed 2013·Granted Jul 1, 2014·1 cites·15 claims
- 1647US10970446B1Automated pipeline insertion on a busXILINX INC·Filed 2018·Granted Apr 6, 2021·0 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →