Inventor · disambiguated record
Johann Leyrer
Also filed as: LEYRER JOHANN
8 granted patents·347 citations·filing 2001–2009
88Inventor score
Top patents by PatentIndex Score
8 records- 0195US6898770B2Split and merge design flow concept for fast turnaround time of circuit layout designLSI LOGIC CORP·Filed 2003·Granted May 24, 2005·235 cites·15 claims
- 0288US7321254B2On-chip automatic process variation, supply voltage variation, and temperature deviation (PVT) compensation methodLSI LOGIC CORP·Filed 2004·Granted Jan 22, 2008·39 cites·4 claims
- 0381US6608365B1Low leakage PMOS on-chip decoupling capacitor cells compatible with standard CMOS cellsLSI LOGIC CORP·Filed 2002·Granted Aug 19, 2003·29 cites·16 claims
- 0478US7334207B2Automatic placement based ESD protection insertionLSI LOGIC CORP·Filed 2005·Granted Feb 19, 2008·9 cites·17 claims
- 0570US6532577B1Timing driven interconnect analysisLSI LOGIC CORP·Filed 2001·Granted Mar 11, 2003·17 cites·30 claims
- 0667US6788098B1Test structures for simultaneous switching output (SSO) analysisLSI LOGIC CORP·Filed 2003·Granted Sep 7, 2004·17 cites·20 claims
- 0758US8332801B2Special engineering change order cellsDIRKS JUERGEN·Filed 2009·Granted Dec 11, 2012·1 cites·18 claims
- 0847US7634748B2Special engineering change order cellsLSI CORP·Filed 2004·Granted Dec 15, 2009·0 cites·20 claims
Join the waitlist — get patent alerts
Get an alert when Johann Leyrer files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →