Inventor · disambiguated record
John D. Heightley
Also filed as: HEIGHTLEY JOHN · HEIGHTLEY JOHN D
18 granted patents·2 pending applications·329 citations·filing 1980–2008
95Inventor score
Files withPROMOS TECHNOLOGIES INC6MOSEL VITELIC INC5PROMOS TECHNOLOGIES PTE LTD3SONY CORP2UNITED MEMORIES INC2
Top patents by PatentIndex Score
20 records- 0195US4355377AAsynchronously equillibrated and pre-charged static ramINMOS CORP·Filed 1980·Granted Oct 19, 1982·89 cites·12 claims
- 0290US6415374B1System and method for supporting sequential burst counts in double data rate (DDR) synchronous dynamic random access memories (SDRAM)MOSEL VITELIC INC·Filed 2000·Granted Jul 2, 2002·57 cites·17 claims
- 0383US7474136B2Use of multiple voltage controlled delay lines for precise alignment and duty cycle control of the data output of a DDR memory devicePROMOS TECHNOLOGIES PTE LTD·Filed 2007·Granted Jan 6, 2009·15 cites·20 claims
- 0479US4363111ADummy cell arrangement for an MOS memoryHEIGHTLEY JOHN D·Filed 1980·Granted Dec 7, 1982·35 cites·10 claims
- 0574US7518425B2Circuit and technique for adjusting and accurately controlling clock duty cycles in integrated circuit devicesPROMOS TECHNOLOGIES PTE LTD·Filed 2007·Granted Apr 14, 2009·7 cites·31 claims
- 0673US6469559B2System and method for eliminating pulse width variations in digital delay linesMOSEL VITELIC INC·Filed 2001·Granted Oct 22, 2002·14 cites·17 claims
- 0772US6445621B1Dynamic data amplifier with built-in voltage level shiftingMOSEL VITELIC INC·Filed 2000·Granted Sep 3, 2002·21 cites·31 claims
- 0870US6339541B1Architecture for high speed memory circuit having a relatively large number of internal data linesUNITED MEMORIES INC·Filed 2000·Granted Jan 15, 2002·14 cites·40 claims
- 0965US6359487B1System and method of compensating for non-linear voltage-to-delay characteristics in a voltage controlled delay lineMOSEL VITELIC INC·Filed 2000·Granted Mar 19, 2002·14 cites·21 claims
- 1065US6339354B1System and method for eliminating pulse width variations in digital delay linesMOSEL VITELIC INC·Filed 2000·Granted Jan 15, 2002·10 cites·14 claims
- 1163US7876137B2Configurable architecture hybrid analog/digital delay locked loop (DLL) and technique with fast open loop digital locking for integrated circuit devicesPROMOS TECHNOLOGIES PTE LTD·Filed 2008·Granted Jan 25, 2011·5 cites·19 claims
- 1260US6741488B1Multi-bank memory array architecture utilizing topologically non-uniform blocks of sub-arrays and input/output assignments in an integrated circuit memory devicePROMOS TECHNOLOGIES INC·Filed 2002·Granted May 25, 2004·10 cites·22 claims
- 1358US7071745B2Voltage-controlled analog delay locked loopPROMOS TECHNOLOGIES INC·Filed 2004·Granted Jul 4, 2006·10 cites·21 claims
- 1454US7102439B2Low voltage differential amplifier circuit and a sampled low power bias control technique enabling accommodation of an increased range of input levelsPROMOS TECHNOLOGIES INC·Filed 2004·Granted Sep 5, 2006·7 cites·10 claims
- 1554US6434069B1Two-phase charge-sharing data latch for memory circuitUNITED MEMORIES INC·Filed 2000·Granted Aug 13, 2002·8 cites·4 claims
- 1651US7167052B2Low voltage differential amplifier circuit for wide voltage range operationPROMOS TECHNOLOGIES INC·Filed 2004·Granted Jan 23, 2007·6 cites·21 claims
- 1745US7061322B2Low voltage differential amplifier circuit and bias control technique enabling accommodation of an increased range of input levelsPROMOS TECHNOLOGIES INC·Filed 2004·Granted Jun 13, 2006·4 cites·24 claims
- 1843US7218564B2Dual equalization devices for long data line pairsPROMOS TECHNOLOGIES INC·Filed 2004·Granted May 15, 2007·3 cites·20 claims
- 1936US2007103124A1System and method for controlling the drive strength of output drivers in integrated circuit devicesSONY CORP·Filed 2005·Application pending·0 cites
- 2036US2007096787A1Method for improving the timing resolution of DLL controlled delay linesSONY CORP·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →