Inventor · disambiguated record
Shih-Hsiung S. Tung
Also filed as: TUNG SHIH-HSIUNG · TUNG SHIH-HSIUNG S · TUNG SHIH-HSIUNG STEPHEN · TUNG SHIH-HSIUNG STEVE
32 granted patents·513 citations·filing 1991–2019
97Inventor score
Technology areasG06F
Top patents by PatentIndex Score
32 records- 0195US10324856B2Address translation for sending real address to memory subsystem in effective address based load-store unitIBM·Filed 2017·Granted Jun 18, 2019·14 cites·7 claims
- 0295US10310988B2Address translation for sending real address to memory subsystem in effective address based load-store unitIBM·Filed 2017·Granted Jun 4, 2019·13 cites·13 claims
- 0393US10417002B2Hazard detection of out-of-order execution of load and store instructions in processors without using real addressesIBM·Filed 2017·Granted Sep 17, 2019·9 cites·17 claims
- 0490US10977047B2Hazard detection of out-of-order execution of load and store instructions in processors without using real addressesIBM·Filed 2019·Granted Apr 13, 2021·5 cites·17 claims
- 0590US7254678B2Enhanced STCX design to improve subsequent load efficiencyIBM·Filed 2005·Granted Aug 7, 2007·38 cites·20 claims
- 0685US7949859B2Mechanism for avoiding check stops in speculative accesses while operating in real modeIBM·Filed 2008·Granted May 24, 2011·13 cites·2 claims
- 0779US9086987B2Detection of conflicts between transactions and page shootdownsIBM·Filed 2012·Granted Jul 21, 2015·5 cites·17 claims
- 0873US8086801B2Loading data to vector renamed register from across multiple cache linesHRUSECKY DAVID A·Filed 2009·Granted Dec 27, 2011·8 cites·20 claims
- 0973US6085291ASystem and method for selectively controlling fetching and prefetching of data to a processorIBM·Filed 1995·Granted Jul 4, 2000·67 cites·20 claims
- 1072US7370177B2Mechanism for avoiding check stops in speculative accesses while operating in real modeIBM·Filed 2003·Granted May 6, 2008·15 cites·3 claims
- 1162US11157415B2Operation of a multi-slice processor implementing a unified page walk cacheIBM·Filed 2019·Granted Oct 26, 2021·0 cites·17 claims
- 1261US6112297AApparatus and method for processing misaligned load instructions in a processor supporting out of order executionIBM·Filed 1998·Granted Aug 29, 2000·39 cites·9 claims
- 1359US10824494B2Operation of a multi-slice processor implementing exception handling in a nested translation environmentIBM·Filed 2018·Granted Nov 3, 2020·0 cites·20 claims
- 1459US6148394AApparatus and method for tracking out of order load instructions to avoid data coherency violations in a processorIBM·Filed 1998·Granted Nov 14, 2000·37 cites·7 claims
- 1557US10664275B2Speeding up younger store instruction execution after a sync instructionIBM·Filed 2018·Granted May 26, 2020·0 cites·21 claims
- 1657US6275918B1Obtaining load target operand pre-fetch address from history table information upon incremented number of access indicator thresholdIBM·Filed 1999·Granted Aug 14, 2001·32 cites·17 claims
- 1756US6463514B1Method to arbitrate for a cache blockIBM·Filed 1998·Granted Oct 8, 2002·30 cites·17 claims
- 1856US6108753ACache error retry techniqueIBM·Filed 1998·Granted Aug 22, 2000·35 cites·8 claims
- 1955US5802567AMechanism for managing offset and aliasing conditions within a content-addressable memory-based cache memoryIBM·Filed 1996·Granted Sep 1, 1998·30 cites·10 claims
- 2054US10042691B2Operation of a multi-slice processor implementing exception handling in a nested translation environmentIBM·Filed 2016·Granted Aug 7, 2018·0 cites·20 claims
- 2154US6430680B1Processor and method of prefetching data based upon a detected strideIBM·Filed 1998·Granted Aug 6, 2002·29 cites·16 claims
- 2252US10534715B2Operation of a multi-slice processor implementing a unified page walk cacheIBM·Filed 2016·Granted Jan 14, 2020·0 cites·15 claims
- 2351US6202128B1Method and system for pre-fetch cache interrogation using snoop portIBM·Filed 1998·Granted Mar 13, 2001·24 cites·10 claims
- 2449US10318419B2Flush avoidance in a load store unitIBM·Filed 2016·Granted Jun 11, 2019·0 cites·20 claims
- 2549US6240487B1Integrated cache buffersIBM·Filed 1998·Granted May 29, 2001·22 cites·16 claims
- 2648US6446170B1Efficient store machine in cache based microprocessorIBM·Filed 1999·Granted Sep 3, 2002·20 cites·17 claims
- 2744US10067765B2Speeding up younger store instruction execution after a sync instructionEISEN SUSAN E·Filed 2012·Granted Sep 4, 2018·0 cites·20 claims
- 2844US9086986B2Detection of conflicts between transactions and page shootdownsCAIN III HAROLD W·Filed 2012·Granted Jul 21, 2015·0 cites·12 claims
- 2939US5319761ADirectory look-aside table for a virtual storage system including means for minimizing synonym entriesIBM·Filed 1991·Granted Jun 7, 1994·13 cites·9 claims
- 3038US6041390AToken mechanism for cache-line replacement within a cache memory having redundant cache linesIBM·Filed 1996·Granted Mar 21, 2000·9 cites·14 claims
- 3132US6304939B1Token mechanism for cache-line replacement within a cache memory having redundant cache linesIBM·Filed 1999·Granted Oct 16, 2001·3 cites·11 claims
- 3231US6298417B1Pipelined cache memory deallocation and storebackIBM·Filed 1998·Granted Oct 2, 2001·3 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →