Inventor · disambiguated record
Simeon Realov
Also filed as: REALOV SIMEON DIMITROV · REALOV Simeon
16 granted patents·3 pending applications·36 citations·filing 2016–2024
90Inventor score
Files withINTEL CORP19
Top patents by PatentIndex Score
19 records- 0193US10473718B2Multibit vectored sequential with scanINTEL CORP·Filed 2017·Granted Nov 12, 2019·4 cites·22 claims
- 0293US9859876B1Shared keeper and footer flip-flopINTEL CORP·Filed 2016·Granted Jan 2, 2018·9 cites·20 claims
- 0391US10193536B2Shared keeper and footer flip-flopINTEL CORP·Filed 2018·Granted Jan 29, 2019·6 cites·19 claims
- 0491US9985612B2Time borrowing flip-flop with clock gating scan multiplexerINTEL CORP·Filed 2016·Granted May 29, 2018·4 cites·20 claims
- 0589US10177765B2Integrated clock gate circuit with embedded NORINTEL CORP·Filed 2016·Granted Jan 8, 2019·7 cites·14 claims
- 0688US10491217B2Low-power clock gate circuitINTEL CORP·Filed 2018·Granted Nov 26, 2019·5 cites·17 claims
- 0777US11398814B2Low-power single-edge triggered flip-flop, and time borrowing internally stitched flip-flopINTEL CORP·Filed 2020·Granted Jul 26, 2022·1 cites·16 claims
- 0874US11442103B2Multibit vectored sequential with scanINTEL CORP·Filed 2021·Granted Sep 13, 2022·0 cites·22 claims
- 0970US11757434B2High performance fast Mux-D scan flip-flopINTEL CORP·Filed 2022·Granted Sep 12, 2023·0 cites·17 claims
- 1069US10862462B2Vectored flip-flopINTEL CORP·Filed 2019·Granted Dec 8, 2020·0 cites·20 claims
- 1167US11054470B1Double edge triggered Mux-D scan flip-flopINTEL CORP·Filed 2019·Granted Jul 6, 2021·0 cites·20 claims
- 1264US2021119616A1Vectored flip-flopINTEL CORP·Filed 2020·Application pending·0 cites
- 1361US10498314B2Vectored flip-flopINTEL CORP·Filed 2016·Granted Dec 3, 2019·0 cites·23 claims
- 1460US11009549B2Multibit vectored sequential with scanINTEL CORP·Filed 2019·Granted May 18, 2021·0 cites·24 claims
- 1559US11296681B2High performance fast Mux-D scan flip-flopINTEL CORP·Filed 2019·Granted Apr 5, 2022·0 cites·20 claims
- 1656US10382019B2Time borrowing flip-flop with clock gating scan multiplexerINTEL CORP·Filed 2018·Granted Aug 13, 2019·0 cites·18 claims
- 1756US2025344511A1Architectures and methods for high performance (hp) standard cell circuitsINTEL CORP·Filed 2024·Application pending·0 cites
- 1854US11791819B2Low power flip-flop with reduced parasitic capacitanceINTEL CORP·Filed 2019·Granted Oct 17, 2023·0 cites·20 claims
- 1945US2024007087A1Integrated clock gate with circuitry to facilitate clock frequency divisionINTEL CORP·Filed 2022·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →