Inventor · disambiguated record
Runsheng Wang
Also filed as: WANG RUNSHENG
14 granted patents·6 pending applications·61 citations·filing 2010–2024
90Inventor score
Files withHUANG RU13UNIV BEIJING4AN XIA1CADENCE DESIGN SYSTEMS INC1UNIV PEKING SHENZHEN GRADUATE SCHOOL1
Top patents by PatentIndex Score
20 records- 0190US9018968B2Method for testing density and location of gate dielectric layer trap of semiconductor deviceHUANG RU·Filed 2012·Granted Apr 28, 2015·17 cites·6 claims
- 0284US8564031B2High voltage-resistant lateral double-diffused transistor based on nanowire deviceHUANG RU·Filed 2011·Granted Oct 22, 2013·9 cites·7 claims
- 0384US8513067B2Fabrication method for surrounding gate silicon nanowire transistor with air as spacersHUANG RU·Filed 2011·Granted Aug 20, 2013·10 cites·9 claims
- 0478US10621386B1Method of bias temperature instability calculation and prediction for MOSFET and FinFETCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Apr 14, 2020·5 cites·19 claims
- 0576US8372752B1Method for fabricating ultra-fine nanowireUNIV BEIJING·Filed 2012·Granted Feb 12, 2013·5 cites·6 claims
- 0671US8288238B2Method for fabricating a tunneling field-effect transistorHUANG RU·Filed 2010·Granted Oct 16, 2012·5 cites·10 claims
- 0768US8563370B2Method for fabricating surrounding-gate silicon nanowire transistor with air sidewallsHUANG RU·Filed 2011·Granted Oct 22, 2013·3 cites·9 claims
- 0867US9478641B2Method for fabricating FinFET with separated double gates on bulk siliconUNIV BEIJING·Filed 2012·Granted Oct 25, 2016·2 cites·4 claims
- 0962US8901644B2Field effect transistor with a vertical channel and fabrication method thereofHUANG RU·Filed 2011·Granted Dec 2, 2014·2 cites·7 claims
- 1059US8866507B2Method for testing trap density of gate dielectric layer in semiconductor device having no substrate contactHUANG RU·Filed 2011·Granted Oct 21, 2014·1 cites·7 claims
- 1156US9034702B2Method for fabricating silicon nanowire field effect transistor based on wet etchingHUANG RU·Filed 2011·Granted May 19, 2015·1 cites·8 claims
- 1256US8592276B2Fabrication method of vertical silicon nanowire field effect transistorHUANG RU·Filed 2011·Granted Nov 26, 2013·1 cites·9 claims
- 1351US2024273274A1Method for establishing transistor statistical model based on artificial neural network systemUNIV PEKING SHENZHEN GRADUATE SCHOOL·Filed 2024·Application pending·0 cites
- 1441US2015140758A1Method for fabricating finfet on germanium or group iii-v semiconductor substrateUNIV BEIJING·Filed 2013·Application pending·0 cites
- 1540US8722312B2Method for fabricating semiconductor nano circular ringHUANG RU·Filed 2011·Granted May 13, 2014·0 cites·7 claims
- 1638US9099500B2Programmable array of silicon nanowire field effect transistor and method for fabricating the sameHUANG RU·Filed 2011·Granted Aug 4, 2015·0 cites·20 claims
- 1736US2013130503A1Method for fabricating ultra-fine nanowireHUANG RU·Filed 2012·Application pending·0 cites
- 1836US2016153923A1Method for extracting trap time constant of gate dielectric layer in semiconductor deviceUNIV BEIJING·Filed 2014·Application pending·0 cites
- 1934US2012238097A1Method for fabricating fine lineHUANG RU·Filed 2011·Application pending·0 cites
- 2031US2012264311A1Surface treatment method for germanium based deviceAN XIA·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →