Inventor · disambiguated record
Lionel Chien Hui Tay
Also filed as: TAY LIONEL CHIEN HUI
110 granted patents·6 pending applications·823 citations·filing 2006–2016
99Inventor score
Files withSTATS CHIPPAC LTD46CAMACHO ZIGMUND RAMIREZ26CAMACHO ZIGMUND R13TAY LIONEL CHIEN HUI12BATHAN HENRY DESCALZO7
Top patents by PatentIndex Score
116 records- 0199US7517733B2Leadframe design for QFN package with top terminal leadsSTATS CHIPPAC LTD·Filed 2007·Granted Apr 14, 2009·125 cites·22 claims
- 0298US8940636B2Through hole vias at saw streets including protrusions or recesses for interconnectionPAGAILA REZA A·Filed 2011·Granted Jan 27, 2015·39 cites·21 claims
- 0398US8420447B2Integrated circuit packaging system with flipchip leadframe and method of manufacture thereofTAY LIONEL CHIEN HUI·Filed 2011·Granted Apr 16, 2013·80 cites·20 claims
- 0497US7915716B2Integrated circuit package system with leadframe arraySTATS CHIPPAC LTD·Filed 2007·Granted Mar 29, 2011·62 cites·18 claims
- 0597US7851246B2Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of the deviceSTATS CHIPPAC LTD·Filed 2007·Granted Dec 14, 2010·40 cites·18 claims
- 0695US7888181B2Method of forming a wafer level package with RDL interconnection over encapsulant between bump and semiconductor dieSTATS CHIPPAC LTD·Filed 2008·Granted Feb 15, 2011·25 cites·23 claims
- 0794US8884418B2Semiconductor device and method of forming PIP with inner known good die interconnected with conductive bumpsCAMACHO ZIGMUND R·Filed 2012·Granted Nov 11, 2014·15 cites·25 claims
- 0893US7964450B2Wirebondless wafer level package with plated bumps and interconnectsSTATS CHIPPAC LTD·Filed 2008·Granted Jun 21, 2011·22 cites·36 claims
- 0992US8035207B2Stackable integrated circuit package system with recessSTATS CHIPPAC LTD·Filed 2006·Granted Oct 11, 2011·23 cites·20 claims
- 1091US7790576B2Semiconductor device and method of forming through hole vias in die extension region around periphery of dieSTATS CHIPPAC LTD·Filed 2007·Granted Sep 7, 2010·15 cites·18 claims
- 1190US7838395B2Semiconductor wafer level interconnect package utilizing conductive ring and pad for separate voltage supplies and method of making the sameSTATS CHIPPAC LTD·Filed 2007·Granted Nov 23, 2010·15 cites·24 claims
- 1289US8097943B2Semiconductor device and method of forming wafer level ground plane and power ringBADAKERE GURUPRASAD G·Filed 2010·Granted Jan 17, 2012·11 cites·24 claims
- 1388US7977780B2Multi-layer package-on-package systemSTATS CHIPPAC LTD·Filed 2008·Granted Jul 12, 2011·16 cites·20 claims
- 1487US9922955B2Semiconductor device and method of forming package-on-package structure electrically interconnected through TSV in WLCSPCAMACHO ZIGMUND R·Filed 2010·Granted Mar 20, 2018·9 cites·17 claims
- 1584US8354742B2Method and apparatus for a package having multiple stacked dieSTATS CHIPPAC LTD·Filed 2008·Granted Jan 15, 2013·11 cites·30 claims
- 1684US8043894B2Integrated circuit package system with redistribution layerSTATS CHIPPAC LTD·Filed 2008·Granted Oct 25, 2011·11 cites·20 claims
- 1784US7714419B2Integrated circuit package system with shieldingSTATS CHIPPAC LTD·Filed 2007·Granted May 11, 2010·13 cites·17 claims
- 1883US8022539B2Integrated circuit packaging system with increased connectivity and method of manufacture thereofSTATS CHIPPAC LTD·Filed 2008·Granted Sep 20, 2011·9 cites·7 claims
- 1983US7919850B2Integrated circuit packaging system with exposed terminal interconnects and method of manufacturing thereofSTATS CHIPPAC LTD·Filed 2008·Granted Apr 5, 2011·12 cites·20 claims
- 2083US7750451B2Multi-chip package system with multiple substratesSTATS CHIPPAC LTD·Filed 2007·Granted Jul 6, 2010·11 cites·20 claims
- 2182US9337161B2Integrated circuit package system with removable backing element having plated terminal leads and method of manufacture thereofSTATS CHIPPAC LTD·Filed 2014·Granted May 10, 2016·4 cites·21 claims
- 2282US8241954B2Wafer level die integration and methodCAMACHO ZIGMUND R·Filed 2007·Granted Aug 14, 2012·9 cites·24 claims
- 2381US8283209B2Semiconductor device and method of forming PiP with inner known good die interconnected with conductive bumpsCAMACHO ZIGMUND R·Filed 2009·Granted Oct 9, 2012·7 cites·25 claims
- 2481US8273602B2Integrated circuit package system with integration portBATHAN HENRY DESCALZO·Filed 2008·Granted Sep 25, 2012·9 cites·20 claims
- 2581US8203214B2Integrated circuit package in package system with adhesiveless package attachBATHAN HENRY DESCALZO·Filed 2007·Granted Jun 19, 2012·7 cites·20 claims
- 2680US8344495B2Integrated circuit packaging system with interconnect and method of manufacture thereofSTATS CHIPPAC LTD·Filed 2009·Granted Jan 1, 2013·9 cites·18 claims
- 2780US8072047B2Integrated circuit package system with shield and tie barCAMACHO ZIGMUND RAMIREZ·Filed 2008·Granted Dec 6, 2011·9 cites·20 claims
- 2880US7842607B2Semiconductor device and method of providing a thermal dissipation path through RDL and conductive viaSTATS CHIPPAC LTD·Filed 2008·Granted Nov 30, 2010·8 cites·19 claims
- 2979US9142514B2Semiconductor device and method of forming wafer level die integrationCAMACHO ZIGMUND R·Filed 2012·Granted Sep 22, 2015·4 cites·20 claims
- 3079US8072079B2Through hole vias at saw streets including protrusions or recesses for interconnectionPAGAILA REZA A·Filed 2008·Granted Dec 6, 2011·7 cites·24 claims
- 3179US7911067B2Semiconductor package system with die support padSTATS CHIPPAC LTD·Filed 2008·Granted Mar 22, 2011·6 cites·10 claims
- 3278US8134242B2Integrated circuit package system with concave terminalCAMACHO ZIGMUND RAMIREZ·Filed 2008·Granted Mar 13, 2012·7 cites·20 claims
- 3377US8493748B2Packaging system with hollow package and method for the sameCAMACHO ZIGMUND RAMIREZ·Filed 2007·Granted Jul 23, 2013·7 cites·18 claims
- 3477US8039302B2Semiconductor package and method of forming similar structure for top and bottom bonding padsSTATS CHIPPAC LTD·Filed 2007·Granted Oct 18, 2011·6 cites·22 claims
- 3577US7977782B2Integrated circuit package system with dual connectivitySTATS CHIPPAC LTD·Filed 2007·Granted Jul 12, 2011·7 cites·18 claims
- 3677US7763493B2Integrated circuit package system with top and bottom terminalsSTATS CHIPPAC LTD·Filed 2007·Granted Jul 27, 2010·7 cites·20 claims
- 3776US8518749B2Semiconductor device and method of forming prefabricated heat spreader frame with embedded semiconductor dieDAHILIG FREDERICK R·Filed 2009·Granted Aug 27, 2013·5 cites·27 claims
- 3876US8502376B2Wirebondless wafer level package with plated bumps and interconnectsCAMACHO ZIGMUND R·Filed 2011·Granted Aug 6, 2013·3 cites·28 claims
- 3975US8941219B2Etched recess package on package systemCAMACHO ZIGMUND RAMIREZ·Filed 2011·Granted Jan 27, 2015·3 cites·10 claims
- 4075US8722457B2System and apparatus for wafer level integration of componentsCAMACHO ZIGMUND R·Filed 2007·Granted May 13, 2014·6 cites·25 claims
- 4175US8586422B2Optical semiconductor device having pre-molded leadframe with window and method thereforCAMACHO ZIGMUND R·Filed 2012·Granted Nov 19, 2013·3 cites·19 claims
- 4275US8304869B2Fan-in interposer on lead frame for an integrated circuit package on package systemCAMACHO ZIGMUND RAMIREZ·Filed 2008·Granted Nov 6, 2012·6 cites·20 claims
- 4375US8216883B2Method for manufacturing semiconductor package system with die support padCAMACHO ZIGMUND RAMIREZ·Filed 2011·Granted Jul 10, 2012·3 cites·10 claims
- 4475US7960815B2Leadframe design for QFN package with top terminal leadsSTATS CHIPPAC LTD·Filed 2009·Granted Jun 14, 2011·5 cites·25 claims
- 4575US7915724B2Integrated circuit packaging system with base structure deviceSTATS CHIPPAC LTD·Filed 2007·Granted Mar 29, 2011·6 cites·20 claims
- 4675US7759806B2Integrated circuit package system with multiple device unitsSTATS CHIPPAC LTD·Filed 2007·Granted Jul 20, 2010·5 cites·12 claims
- 4775US7732901B2Integrated circuit package system with isloated leadsSTATS CHIPPAC LTD·Filed 2008·Granted Jun 8, 2010·6 cites·20 claims
- 4874US7977779B2Mountable integrated circuit package-in-package systemSTATS CHIPPAC LTD·Filed 2008·Granted Jul 12, 2011·5 cites·20 claims
- 4974US7855444B2Mountable integrated circuit package system with substrateSTATS CHIPPAC LTD·Filed 2008·Granted Dec 21, 2010·6 cites·17 claims
- 5073US8362601B2Wire-on-lead package system having leadfingers positioned between paddle extensions and method of manufacture thereofSTATS CHIPPAC LTD·Filed 2008·Granted Jan 29, 2013·5 cites·20 claims
Showing the top 50 of 116 patent records by PatentIndex Score.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →