Inventor · disambiguated record
Tsai-Sheng Chen
Also filed as: CHEN TSAI-SHENG
14 granted patents·1 pending application·22 citations·filing 1998–2022
87Inventor score
Files withVIA TECH INC7SHANGHAI ZHAOXIN SEMICONDUCTOR CO LTD5CHANG NAI-SHUNG1VIA ALLIANCE SEMICONDUCTOR CO LTD1VIA TECHNOLOGYIES INC1
Top patents by PatentIndex Score
15 records- 0179US10568199B2Printed circuit board and semiconductor package structureSHANGHAI ZHAOXIN SEMICONDUCTOR CO LTD·Filed 2017·Granted Feb 18, 2020·2 cites·23 claims
- 0259US11362464B2Contact arrangement, circuit board, and electronic assemblySHANGHAI ZHAOXIN SEMICONDUCTOR CO LTD·Filed 2020·Granted Jun 14, 2022·0 cites·19 claims
- 0359US11316305B2Contact arrangement, circuit board, and electronic assemblySHANGHAI ZHAOXIN SEMICONDUCTOR CO LTD·Filed 2020·Granted Apr 26, 2022·0 cites·20 claims
- 0458US10568200B2Printed circuit board and semiconductor package structureSHANGHAI ZHAOXIN SEMICONDUCTOR CO LTD·Filed 2017·Granted Feb 18, 2020·0 cites·17 claims
- 0558US10568198B2Printed circuit board and semiconductor package structureSHANGHAI ZHAOXIN SEMICONDUCTOR CO LTD·Filed 2017·Granted Feb 18, 2020·0 cites·19 claims
- 0656US12191242B2Contact arrangement and electronic assemblyVIA TECH INC·Filed 2022·Granted Jan 7, 2025·0 cites·30 claims
- 0755US6946731B2Layout structure for providing stable power source to a main bridge chip substrate and a motherboardVIA TECH INC·Filed 2002·Granted Sep 20, 2005·5 cites·11 claims
- 0853US6877102B2Chipset supporting multiple CPU's and layout method thereofVIA TECH INC·Filed 2001·Granted Apr 5, 2005·3 cites·16 claims
- 0951US6981162B2Suspend-to-RAM controlling circuitVIA TECH INC·Filed 2002·Granted Dec 27, 2005·2 cites·17 claims
- 1049US6377510B2Memory control system for controlling write-enable signalsVIA TECHNOLOGYIES INC·Filed 2001·Granted Apr 23, 2002·4 cites·16 claims
- 1148US9198286B2Circuit board and electronic assemblyVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Nov 24, 2015·0 cites·18 claims
- 1246US6794744B2Layout structure and method for supporting two different package techniques of CPUVIA TECH INC·Filed 2002·Granted Sep 21, 2004·1 cites·27 claims
- 1344US6888071B2Layout structure and method for supporting two different package techniques of CPUVIA TECH INC·Filed 2004·Granted May 3, 2005·0 cites·11 claims
- 1443US2005263849A1Layout structure for providing stable power source to a main bridge chip substrate and a motherboardCHANG NAI-SHUNG·Filed 2005·Application pending·0 cites
- 1533US6134701AComputer motherboard with a control chip having specific pin arrangement for fast cache accessVIA TECH INC·Filed 1998·Granted Oct 17, 2000·5 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →