Inventor · disambiguated record
Jesmin Jahan Tithi
Also filed as: TITHI JESMIN JAHAN
5 granted patents·6 pending applications·11 citations·filing 2019–2024
72Inventor score
Files withINTEL CORP11
Top patents by PatentIndex Score
11 records- 0193US11693633B2Methods and apparatus to detect and annotate backedges in a dataflow graphINTEL CORP·Filed 2021·Granted Jul 4, 2023·6 cites·24 claims
- 0279US11782813B2Methods and apparatus to determine refined context for software bug detection and correctionINTEL CORP·Filed 2021·Granted Oct 10, 2023·1 cites·23 claims
- 0377US11029927B2Methods and apparatus to detect and annotate backedges in a dataflow graphINTEL CORP·Filed 2019·Granted Jun 8, 2021·2 cites·24 claims
- 0475US10965536B2Methods and apparatus to insert buffers in a dataflow graphINTEL CORP·Filed 2019·Granted Mar 30, 2021·2 cites·44 claims
- 0553US12386669B2Methods and apparatus to determine execution costINTEL CORP·Filed 2021·Granted Aug 12, 2025·0 cites·21 claims
- 0653US2024241645A1Instruction set architecture and hardware support for hash operationsINTEL CORP·Filed 2024·Application pending·0 cites
- 0750US2024020253A1Instruction set architecture support for data type conversion in near-memory dma operationsINTEL CORP·Filed 2023·Application pending·0 cites
- 0849US2023315451A1Technology to support bitmap manipulation operations using a direct memory access instruction set architectureINTEL CORP·Filed 2023·Application pending·0 cites
- 0948US2023333998A1Instruction set architecture support for conditional direct memory access data movement operationsINTEL CORP·Filed 2023·Application pending·0 cites
- 1047US2023325185A1Methods and apparatus to accelerate matrix operations using direct memory accessINTEL CORP·Filed 2023·Application pending·0 cites
- 1138US2021117807A1Methods and appartus to construct program-derived semantic graphsINTEL CORP·Filed 2020·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →