Inventor · disambiguated record
Harold W. Kennel
Also filed as: KENNEL HAROLD · KENNEL HAROLD W
80 granted patents·14 pending applications·140 citations·filing 2002–2024
98Inventor score
Top patents by PatentIndex Score
94 records- 0194US8896066B2Tin doped III-V material contactsINTEL CORP·Filed 2012·Granted Nov 25, 2014·14 cites·25 claims
- 0293US9570614B2Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxationINTEL CORP·Filed 2013·Granted Feb 14, 2017·14 cites·8 claims
- 0392US9443980B2Pulsed laser anneal process for transistors with partial melt of a raised source-drainINTEL CORP·Filed 2015·Granted Sep 13, 2016·7 cites·15 claims
- 0491US10229997B2Indium-rich NMOS transistor channelsINTEL CORP·Filed 2015·Granted Mar 12, 2019·6 cites·20 claims
- 0590US10892335B2Device isolation by fixed chargeINTEL CORP·Filed 2016·Granted Jan 12, 2021·6 cites·20 claims
- 0690US10446685B2High-electron-mobility transistors with heterojunction dopant diffusion barrierINTEL CORP·Filed 2015·Granted Oct 15, 2019·6 cites·18 claims
- 0790US10186580B2Semiconductor device having germanium active layer with underlying diffusion barrier layerINTEL CORP·Filed 2017·Granted Jan 22, 2019·5 cites·25 claims
- 0889US11581406B2Method of fabricating CMOS FinFETs by selectively etching a strained SiGe layerINTEL CORP·Filed 2021·Granted Feb 14, 2023·1 cites·17 claims
- 0989US10153372B2High mobility strained channels for fin-based NMOS transistorsINTEL CORP·Filed 2014·Granted Dec 11, 2018·5 cites·25 claims
- 1087US9935107B2CMOS FinFET device with dual strained cladding layers on relaxed SiGe fins, and method of fabricating the sameINTEL CORP·Filed 2013·Granted Apr 3, 2018·6 cites·20 claims
- 1182US12255234B2Integrated circuit structures having germanium-based channelsINTEL CORP·Filed 2024·Granted Mar 18, 2025·0 cites·11 claims
- 1281US11257904B2Source-channel junction for III-V metal-oxide-semiconductor field effect transistors (MOSFETs)INTEL CORP·Filed 2018·Granted Feb 22, 2022·2 cites·25 claims
- 1380US11469323B2Ferroelectric gate stack for band-to-band tunneling reductionINTEL CORP·Filed 2018·Granted Oct 11, 2022·2 cites·15 claims
- 1480US10170314B2Pulsed laser anneal process for transistor with partial melt of a raised source-drainINTEL CORP·Filed 2016·Granted Jan 1, 2019·2 cites·20 claims
- 1580US9698265B2Strained channel region transistors employing source and drain stressors and systems including the sameINTEL CORP·Filed 2016·Granted Jul 4, 2017·2 cites·15 claims
- 1679US6800887B1Nitrogen controlled growth of dislocation loop in stress enhanced transistorINTEL CORP·Filed 2003·Granted Oct 5, 2004·17 cites·5 claims
- 1778US11164974B2Channel layer formed in an art trenchINTEL CORP·Filed 2017·Granted Nov 2, 2021·2 cites·18 claims
- 1877US11195919B2Method of fabricating a semiconductor device with strained SiGe fins and a Si cladding layerINTEL CORP·Filed 2018·Granted Dec 7, 2021·1 cites·5 claims
- 1976US12288807B2Amorphization and regrowth of source-drain regions from the bottom-side of a semiconductor assemblyINTEL CORP·Filed 2023·Granted Apr 29, 2025·0 cites·9 claims
- 2076US7758238B2Temperature measurement with reduced extraneous infrared in a processing chamberINTEL CORP·Filed 2008·Granted Jul 20, 2010·8 cites·15 claims
- 2175US11923421B2Integrated circuit structures having germanium-based channelsINTEL CORP·Filed 2022·Granted Mar 5, 2024·0 cites·3 claims
- 2275US9006069B2Pulsed laser anneal process for transistors with partial melt of a raised source-drainJENSEN JACOB·Filed 2011·Granted Apr 14, 2015·3 cites·17 claims
- 2375US2023170388A1Cmos finfet device having strained sige fins and a strained si cladding layer on the nmos channelDAEDALUS PRIME LLC·Filed 2023·Application pending·0 cites
- 2474US9397166B2Strained channel region transistors employing source and drain stressors and systems including the sameLE VAN H·Filed 2011·Granted Jul 19, 2016·3 cites·26 claims
- 2573US11929435B2Ferroelectric gate stack for band-to-band tunneling reductionINTEL CORP·Filed 2022·Granted Mar 12, 2024·0 cites·22 claims
- 2673US7226824B2Nitrogen controlled growth of dislocation loop in stress enhanced transistorINTEL CORP·Filed 2004·Granted Jun 5, 2007·11 cites·11 claims
- 2772US11990476B2Semiconductor nanowire device having (111)-plane channel sidewallsINTEL CORP·Filed 2022·Granted May 21, 2024·0 cites·20 claims
- 2872US7892971B2Sub-second annealing processes for semiconductor devicesINTEL CORP·Filed 2008·Granted Feb 22, 2011·5 cites·15 claims
- 2972US2024258427A1Source or drain structures for germanium n-channel devicesINTEL CORP·Filed 2024·Application pending·0 cites
- 3070US11756998B2Source-channel junction for III-V metal-oxide-semiconductor field effect transistors (MOSFETs)INTEL CORP·Filed 2022·Granted Sep 12, 2023·0 cites·20 claims
- 3170US2024164080A1Channel depopulation for forksheet transistorsINTEL CORP·Filed 2023·Application pending·0 cites
- 3268US10957769B2High-mobility field effect transistors with wide bandgap fin claddingINTEL CORP·Filed 2016·Granted Mar 23, 2021·1 cites·20 claims
- 3367US11476338B2Aluminum indium phosphide subfin germanium channel transistorsINTEL CORP·Filed 2020·Granted Oct 18, 2022·0 cites·20 claims
- 3467US9966440B2Tin doped III-V material contactsINTEL CORP·Filed 2014·Granted May 8, 2018·1 cites·25 claims
- 3566US10546858B2Low damage self-aligned amphoteric FINFET tip dopingINTEL CORP·Filed 2015·Granted Jan 28, 2020·1 cites·12 claims
- 3666US10529808B2Dopant diffusion barrier for source/drain to curb dopant atom diffusionINTEL CORP·Filed 2016·Granted Jan 7, 2020·1 cites·21 claims
- 3765US11101350B2Integrated circuit with germanium-rich channel transistors including one or more dopant diffusion barrier elementsINTEL CORP·Filed 2020·Granted Aug 24, 2021·0 cites·19 claims
- 3865US7187057B2Nitrogen controlled growth of dislocation loop in stress enhanced transistorINTEL CORP·Filed 2004·Granted Mar 6, 2007·7 cites·12 claims
- 3964US2022109072A1Reducing band-to-band tunneling in semiconductor devicesINTEL CORP·Filed 2021·Application pending·0 cites
- 4063US2020381549A1High mobility strained channels for fin-based nmos transistorsINTEL CORP·Filed 2020·Application pending·0 cites
- 4162US10854752B2High mobility strained channels for fin-based NMOS transistorsINTEL CORP·Filed 2018·Granted Dec 1, 2020·0 cites·20 claims
- 4262US9608055B2Semiconductor device having germanium active layer with underlying diffusion barrier layerRACHMADY WILLY·Filed 2011·Granted Mar 28, 2017·1 cites·18 claims
- 4361US10818793B2Indium-rich NMOS transistor channelsINTEL CORP·Filed 2019·Granted Oct 27, 2020·0 cites·20 claims
- 4460US11437472B2Integrated circuit structures having germanium-based channelsINTEL CORP·Filed 2018·Granted Sep 6, 2022·0 cites·20 claims
- 4559US11798991B2Amorphization and regrowth of source-drain regions from the bottom-side of a semiconductor assemblyINTEL CORP·Filed 2019·Granted Oct 24, 2023·0 cites·5 claims
- 4658US10103263B2Strained channel region transistors employing source and drain stressors and systems including the sameINTEL CORP·Filed 2017·Granted Oct 16, 2018·0 cites·19 claims
- 4757US12426342B2Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stabilityINTEL CORP·Filed 2021·Granted Sep 23, 2025·0 cites·8 claims
- 4856US12439669B2Co-deposition of titanium and silicon for improved silicon germanium source and drain contactsINTEL CORP·Filed 2021·Granted Oct 7, 2025·0 cites·20 claims
- 4956US10692973B2Germanium-rich channel transistors including one or more dopant diffusion barrier elementsINTEL CORP·Filed 2017·Granted Jun 23, 2020·0 cites·20 claims
- 5056US10109711B2CMOS FinFET device having strained SiGe fins and a strained Si cladding layer on the NMOS channelINTEL CORP·Filed 2013·Granted Oct 23, 2018·0 cites·10 claims
Showing the top 50 of 94 patent records by PatentIndex Score.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →