Inventor · disambiguated record
Stefanos Kaxiras
Also filed as: KAXIRAS STEFANOS
31 granted patents·4 pending applications·491 citations·filing 1997–2025
97Inventor score
Files withETA SCALE AB10AGERE SYSTEMS INC8SAMSUNG ELECTRONICS CO LTD4ADVANCED RISC MACH LTD3KAXIRAS STEFANOS3
Top patents by PatentIndex Score
35 records- 0191US6658551B1Method and apparatus for identifying splittable packets in a multithreaded VLIW processorAGERE SYSTEMS INC·Filed 2000·Granted Dec 2, 2003·78 cites·17 claims
- 0288US10915466B2System protecting caches from side-channel attacksSAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Feb 9, 2021·5 cites·20 claims
- 0387US7007153B1Method and apparatus for allocating functional units in a multithreaded VLIW processorAGERE SYSTEMS INC·Filed 2000·Granted Feb 28, 2006·50 cites·16 claims
- 0487US6161170AMultiple processor, distributed memory computer with out-of-order processingWISCONSIN ALUMNI RES FOUND·Filed 1999·Granted Dec 12, 2000·102 cites·1 claims
- 0586US9274960B2System and method for simplifying cache coherence using multiple write policiesKAXIRAS STEFANOS·Filed 2013·Granted Mar 1, 2016·14 cites·27 claims
- 0684US6665791B1Method and apparatus for releasing functional units in a multithreaded VLIW processorAGERE SYSTEMS INC·Filed 2000·Granted Dec 16, 2003·39 cites·19 claims
- 0783US7096343B1Method and apparatus for splitting packets in multithreaded VLIW processorAGERE SYSTEMS INC·Filed 2000·Granted Aug 22, 2006·37 cites·16 claims
- 0882US7472302B2Method and apparatus for reducing leakage power in a cache memory using adaptive time-based decayAGERE SYSTEMS INC·Filed 2005·Granted Dec 30, 2008·12 cites·26 claims
- 0981US11119920B2Systems and methods for non-speculative store coalescing and generating atomic write sets using address subsetsETA SCALE AB·Filed 2019·Granted Sep 14, 2021·3 cites·16 claims
- 1078US11068410B2Multi-core computer systems with private/shared cache line indicatorsETA SCALE AB·Filed 2019·Granted Jul 20, 2021·2 cites·11 claims
- 1176US11334485B2System and method for dynamic enforcement of store atomicityETA SCALE AB·Filed 2019·Granted May 17, 2022·2 cites·20 claims
- 1275US10402344B2Systems and methods for direct data access in multi-level cache memory hierarchiesSAMSUNG ELECTRONICS CO LTD·Filed 2014·Granted Sep 3, 2019·3 cites·28 claims
- 1373US11188464B2System and method for self-invalidation, self-downgrade cachecoherence protocolsETA SCALE AB·Filed 2019·Granted Nov 30, 2021·1 cites·20 claims
- 1471US6061776AMultiple processor, distributed memory computer with out-of-order processingWISCONSIN ALUMNI RES FOUND·Filed 1999·Granted May 9, 2000·46 cites·8 claims
- 1569US5943501AMultiple processor, distributed memory computer with out-of-order processingWISCONSIN ALUMNI RES FOUND·Filed 1997·Granted Aug 24, 1999·42 cites·5 claims
- 1667US6983388B2Method and apparatus for reducing leakage power in a cache memory by using a timer control signal that removes power to associated cache linesAGERE SYSTEMS INC·Filed 2001·Granted Jan 3, 2006·13 cites·35 claims
- 1767US6889293B1Directory-based prediction methods and apparatus for shared-memory multiprocessor systemsAGERE SYSTEMS INC·Filed 2000·Granted May 3, 2005·12 cites·34 claims
- 1860US11237966B2System and method for event monitoring in cache coherence protocols without explicit invalidationsETA SCALE AB·Filed 2019·Granted Feb 1, 2022·0 cites·35 claims
- 1960US7573880B2Set-associative memory architecture for routing tablesAGERE SYSTEMS INC·Filed 2004·Granted Aug 11, 2009·7 cites·28 claims
- 2060US2025181716A1Securing computing systems against microarchitectural replay attacksETA SCALE AB·Filed 2025·Application pending·0 cites
- 2155US10671543B2Systems and methods for reducing first level cache energy by eliminating cache address tagsSAMSUNG ELECTRONICS CO LTD·Filed 2014·Granted Jun 2, 2020·0 cites·15 claims
- 2254US10528471B2System and method for self-invalidation, self-downgrade cachecoherence protocolsETA SCALE AB·Filed 2017·Granted Jan 7, 2020·0 cites·16 claims
- 2354US10402331B2Systems and methods for implementing a tag-less shared cache and a larger backing cacheSAMSUNG ELECTRONICS CO LTD·Filed 2015·Granted Sep 3, 2019·0 cites·17 claims
- 2453US2025328311A1Systems and methods for energy-efficient, bit-parallel, multiply-accumulate for artificial intelligence and deep neural networksKAXIRAS STEFANOS·Filed 2025·Application pending·0 cites
- 2551US2021365554A1Securing computing systems against microarchitectural replay attacksETA SCALE AB·Filed 2021·Application pending·0 cites
- 2649US11106468B2System and method for non-speculative reordering of load accessesETA SCALE AB·Filed 2018·Granted Aug 31, 2021·0 cites·14 claims
- 2748US11886881B2Decoupled access-execute processing and prefetching controlADVANCED RISC MACH LTD·Filed 2020·Granted Jan 30, 2024·0 cites·20 claims
- 2847US11899940B2Apparatus and method for handling memory load requestsADVANCED RISC MACH LTD·Filed 2020·Granted Feb 13, 2024·0 cites·16 claims
- 2947US10324861B2Systems and methods for coherence in clustered cache hierarchiesROS ALBERTO·Filed 2016·Granted Jun 18, 2019·0 cites·7 claims
- 3045US10387312B2System and method for event monitoring in cache coherence protocols without explicit invalidationsKAXIRAS STEFANOS·Filed 2015·Granted Aug 20, 2019·0 cites·14 claims
- 3144US12001845B2Decoupled access-execute processingADVANCED RISC MACH LTD·Filed 2020·Granted Jun 4, 2024·0 cites·13 claims
- 3244US5946496ADistributed vector architectureCRAY RESEARCH INC·Filed 1997·Granted Aug 31, 1999·15 cites·17 claims
- 3341US11163576B2Systems and methods for invisible speculative executionETA SCALE AB·Filed 2020·Granted Nov 2, 2021·0 cites·16 claims
- 3437US2003145241A1Method and apparatus for reducing leakage power in a cache memory using adaptive time-based decayFiled 2002·Application pending·0 cites
- 3536US5913069AInterleaving memory in distributed vector architecture multiprocessor systemCRAY RESEARCH INC·Filed 1997·Granted Jun 15, 1999·8 cites·13 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →