Inventor · disambiguated record
Kwang-Lung Lin
Also filed as: LIN KWANG-LUNG
9 granted patents·1 pending application·214 citations·filing 1994–2017
88Inventor score
Top patents by PatentIndex Score
10 records- 0189US10217649B2Semiconductor device package having an underfill barrierADVANCED SEMICONDUCTOR ENG·Filed 2017·Granted Feb 26, 2019·9 cites·20 claims
- 0289US5583073AMethod for producing electroless barrier layer and solder bump on chipNAT SCIENCE COUNCIL·Filed 1995·Granted Dec 10, 1996·118 cites·18 claims
- 0381US9953930B1Semiconductor package structure and method for manufacturing the sameADVANCED SEMICONDUCTOR ENG·Filed 2016·Granted Apr 24, 2018·5 cites·18 claims
- 0478US9443813B1Semiconductor device and method for manufacturing the sameADVANCED SEMICONDUCTOR ENG·Filed 2015·Granted Sep 13, 2016·3 cites·12 claims
- 0569US5795619ASolder bump fabricated method incorporate with electroless deposit and dip solderNAT SCIENCE COUNCIL·Filed 1995·Granted Aug 18, 1998·33 cites·12 claims
- 0659US5578175AProcess for manufacturing iridium and palladium oxides-coated titanium electrode and the electrode produced therebyNAT SCIENCE COUNCIL·Filed 1994·Granted Nov 26, 1996·15 cites·35 claims
- 0755US6153503AContinuous process for producing solder bumps on electrodes of semiconductor chipsNAT SCIENCE COUNCIL·Filed 1998·Granted Nov 28, 2000·29 cites·2 claims
- 0848US9960136B2Semiconductor device and method for manufacturing the sameADVANCED SEMICONDUCTOR ENG·Filed 2016·Granted May 1, 2018·0 cites·13 claims
- 0945US2018021896A1Lead-free solder compositionUNIV NAT CHENG KUNG·Filed 2017·Application pending·0 cites
- 1040US6837947B2Lead-free solderUNIV NAT CHENG KUNG·Filed 2002·Granted Jan 4, 2005·2 cites·2 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →