Inventor · disambiguated record
Steven W. Tomashot
Also filed as: TOMASHOT STEVEN · TOMASHOT STEVEN W · TOMASHOT STEVEN WILLIAM
17 granted patents·1,081 citations·filing 1988–2001
96Inventor score
Files withIBM17
Top patents by PatentIndex Score
17 records- 0195US5787457ACached synchronous DRAM architecture allowing concurrent DRAM operationsIBM·Filed 1996·Granted Jul 28, 1998·260 cites·9 claims
- 0295US5430679AFlexible redundancy architecture and fuse download schemeIBM·Filed 1993·Granted Jul 4, 1995·146 cites·11 claims
- 0395US5001672AVideo ram with external select of active serial access registerIBM·Filed 1989·Granted Mar 19, 1991·133 cites·11 claims
- 0494US6141245AImpedance control using fusesIBM·Filed 1999·Granted Oct 31, 2000·142 cites·31 claims
- 0591US6289413B1Cached synchronous DRAM architecture having a mode register programmable cache policyIBM·Filed 1999·Granted Sep 11, 2001·108 cites·19 claims
- 0689US6438062B1Multiple memory bank command for synchronous DRAMsIBM·Filed 2000·Granted Aug 20, 2002·55 cites·40 claims
- 0787US6434082B1Clocked memory device that includes a programming mechanism for setting write recovery time as a function of the input clockIBM·Filed 2001·Granted Aug 13, 2002·45 cites·19 claims
- 0887US6243283B1Impedance control using fusesIBM·Filed 2000·Granted Jun 5, 2001·42 cites·4 claims
- 0985US6178126B1Memory and system configuration for programming a redundancy address in an electric systemIBM·Filed 2000·Granted Jan 23, 2001·38 cites·32 claims
- 1071US6658604B1Method for testing and guaranteeing that skew between two signals meets predetermined criteriaIBM·Filed 2000·Granted Dec 2, 2003·16 cites·26 claims
- 1171US5065368AVideo ram double buffer select controlIBM·Filed 1989·Granted Nov 12, 1991·27 cites·8 claims
- 1271US4984214AMultiplexed serial register architecture for VRAMIBM·Filed 1989·Granted Jan 8, 1991·27 cites·6 claims
- 1362US6708298B2Method for guaranteeing a minimum data strobe valid window and a minimum data valid window for DDR memory devicesIBM·Filed 2001·Granted Mar 16, 2004·13 cites·19 claims
- 1452US5022006ASemiconductor memory having bit lines with isolation circuits connected between redundant and normal memory cellsIBM·Filed 1988·Granted Jun 4, 1991·12 cites·4 claims
- 1545US5745431AAddress transition detector (ATD) for power conservationIBM·Filed 1996·Granted Apr 28, 1998·11 cites·16 claims
- 1638US5901093ARedundancy architecture and method for block write access cycles permitting defective memory line replacementIBM·Filed 1995·Granted May 4, 1999·6 cites·13 claims
- 1730US6195027B1Capacitive precharging and discharging network for converting N bit input into M bit outputIBM·Filed 1999·Granted Feb 27, 2001·0 cites·39 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →