Inventor · disambiguated record
Paul Ferreira
Also filed as: FERREIRA PAUL · FERREIRA PAUL J
11 granted patents·2 pending applications·40 citations·filing 2002–2020
85Inventor score
Files withST MICROELECTRONICS INC4ST MICROELECTRONICS SA3ZHANG JOHN H3FERREIRA PAUL1ST MICROELECTRONICS CROLLES 21
Top patents by PatentIndex Score
13 records- 0191US8569899B2Device and method for alignment of vertically stacked wafers and dieZHANG JOHN H·Filed 2009·Granted Oct 29, 2013·14 cites·17 claims
- 0274US6689655B2Method for production process for the local interconnection level using a dielectric conducting pair on pairST MICROELECTRONICS SA·Filed 2002·Granted Feb 10, 2004·22 cites·8 claims
- 0371US11205621B2Device and method for alignment of vertically stacked wafers and dieST MICROELECTRONICS INC·Filed 2020·Granted Dec 21, 2021·0 cites·12 claims
- 0469US9324660B2Device and method for alignment of vertically stacked wafers and dieST MICROELECTRONICS INC·Filed 2013·Granted Apr 26, 2016·1 cites·13 claims
- 0560US10615125B2Device and method for alignment of vertically stacked wafers and dieST MICROELECTRONICS INC·Filed 2017·Granted Apr 7, 2020·0 cites·12 claims
- 0657US9870999B2Device and method for alignment of vertically stacked wafers and dieST MICROELECTRONICS INC·Filed 2015·Granted Jan 16, 2018·0 cites·23 claims
- 0751US8603916B2CMP techniques for overlapping layer removalZHANG JOHN H·Filed 2009·Granted Dec 10, 2013·0 cites·37 claims
- 0848US7838407B2Method for protecting the gate of a transistor and corresponding integrated circuitST MICROELECTRONICS CROLLES 2·Filed 2006·Granted Nov 23, 2010·0 cites·21 claims
- 0946US6797597B2Process for treating complementary regions of the surface of a substrate and semiconductor product obtained by this processST MICROELECTRONICS SA·Filed 2002·Granted Sep 28, 2004·3 cites·15 claims
- 1039US8823107B2Method for protecting the gate of a transistor and corresponding integrated circuitFERREIRA PAUL·Filed 2010·Granted Sep 2, 2014·0 cites·20 claims
- 1139US2005059939A1Phacoemulsification needleFiled 2003·Application pending·0 cites
- 1238US6911366B2Method for forming contact openings on a MOS integrated circuitST MICROELECTRONICS SA·Filed 2003·Granted Jun 28, 2005·0 cites·20 claims
- 1336US2012122373A1Precise real time and position low pressure control of chemical mechanical polish (cmp) headZHANG JOHN H·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →