Inventor · disambiguated record
Sailesh Kottapalli
Also filed as: KOTTAPALLI SAILESH
33 granted patents·12 pending applications·322 citations·filing 1998–2020
97Inventor score
Top patents by PatentIndex Score
45 records- 0196US9858167B2Monitoring the operation of a processorINTEL CORP·Filed 2015·Granted Jan 2, 2018·16 cites·5 claims
- 0289US6898694B2High instruction fetch bandwidth in multithread processor using temporary instruction cache to deliver portion of cache line in subsequent clock cycleINTEL CORP·Filed 2001·Granted May 24, 2005·59 cites·9 claims
- 0386US8473963B2Synchronizing multiple threads efficientlyKOTTAPALLI SAILESH·Filed 2011·Granted Jun 25, 2013·7 cites·19 claims
- 0484US7062933B2Separate thermal and electrical throttling limits in processorsINTEL CORP·Filed 2004·Granted Jun 20, 2006·37 cites·25 claims
- 0583US7984248B2Transaction based shared data operations in a multiprocessor environmentINTEL CORP·Filed 2004·Granted Jul 19, 2011·27 cites·35 claims
- 0682US8656115B2Extending a cache coherency snoop broadcast protocol with directory informationKOTTAPALLI SAILESH·Filed 2010·Granted Feb 18, 2014·6 cites·20 claims
- 0776US7149880B2Method and apparatus for instruction pointer storage element configuration in a simultaneous multithreaded processorINTEL CORP·Filed 2000·Granted Dec 12, 2006·19 cites·22 claims
- 0875US8176266B2Transaction based shared data operations in a multiprocessor environmentKOTTAPALLI SAILESH·Filed 2010·Granted May 8, 2012·3 cites·9 claims
- 0975US6304960B1Validating prediction for branches in a cluster via comparison of predicted and condition selected tentative target addresses and validation of branch conditionsINTEL CORP·Filed 1998·Granted Oct 16, 2001·70 cites·25 claims
- 1073US9423959B2Method and apparatus for store durability and ordering in a persistent memory architectureINTEL CORP·Filed 2013·Granted Aug 23, 2016·3 cites·18 claims
- 1171US8458412B2Transaction based shared data operations in a multiprocessor environmentKOTTAPALLI SAILESH·Filed 2011·Granted Jun 4, 2013·2 cites·16 claims
- 1269US9405595B2Synchronizing multiple threads efficientlyINTEL CORP·Filed 2014·Granted Aug 2, 2016·1 cites·14 claims
- 1367US7500240B2Apparatus and method for scheduling threads in multi-threading processorsINTEL CORP·Filed 2002·Granted Mar 3, 2009·13 cites·15 claims
- 1466US11048588B2Monitoring the operation of a processorINTEL CORP·Filed 2020·Granted Jun 29, 2021·0 cites·8 claims
- 1566US10387151B2Processor and method for tracking progress of gathering/scattering data element pairs in different cache memory banksHALL JONATHAN C·Filed 2011·Granted Aug 20, 2019·3 cites·12 claims
- 1666US7669009B2Method and apparatus for run-ahead victim selection to reduce undesirable replacement behavior in inclusive cachesINTEL CORP·Filed 2004·Granted Feb 23, 2010·11 cites·36 claims
- 1764US7996644B2Fair sharing of a cache in a multi-core/multi-threaded processor by dynamically partitioning of the cacheINTEL CORP·Filed 2004·Granted Aug 9, 2011·9 cites·39 claims
- 1863US9201748B2Virtual device sparingMORRIS BRIAN S·Filed 2012·Granted Dec 1, 2015·2 cites·22 claims
- 1963US7937709B2Synchronizing multiple threads efficientlyINTEL CORP·Filed 2004·Granted May 3, 2011·6 cites·21 claims
- 2060US10599547B2Monitoring the operation of a processorINTEL CORP·Filed 2017·Granted Mar 24, 2020·0 cites·13 claims
- 2159US8205204B2Apparatus and method for scheduling threads in multi-threading processorsSHOEMAKER KEN·Filed 2009·Granted Jun 19, 2012·2 cites·12 claims
- 2258US9298629B2Extending a cache coherency snoop broadcast protocol with directory informationINTEL CORP·Filed 2014·Granted Mar 29, 2016·0 cites·20 claims
- 2358US7496732B2Method and apparatus for results speculation under run-ahead executionINTEL CORP·Filed 2003·Granted Feb 24, 2009·9 cites·20 claims
- 2457US8301907B2Supporting advanced RAS features in a secured computing systemNATU MAHESH S·Filed 2007·Granted Oct 30, 2012·1 cites·12 claims
- 2557US7401211B2Method for converting pipeline stalls caused by instructions with long latency memory accesses to pipeline flushes in a multithreaded processorINTEL CORP·Filed 2000·Granted Jul 15, 2008·6 cites·11 claims
- 2656US8918592B2Extending a cache coherency snoop broadcast protocol with directory informationINTEL CORP·Filed 2013·Granted Dec 23, 2014·0 cites·16 claims
- 2756US8819684B2Synchronizing multiple threads efficientlyINTEL CORP·Filed 2013·Granted Aug 26, 2014·0 cites·13 claims
- 2855US7181590B2Method for page sharing in a processor with multiple threads and pre-validated cachesINTEL CORP·Filed 2003·Granted Feb 20, 2007·6 cites·34 claims
- 2951US7149881B2Method and apparatus for improving dispersal performance in a processor through the use of no-op portsINTEL CORP·Filed 2004·Granted Dec 12, 2006·3 cites·17 claims
- 3050US9436605B2Cache coherency apparatus and method minimizing memory writeback operationsINTEL CORP·Filed 2013·Granted Sep 6, 2016·0 cites·19 claims
- 3150US2008215864A1Method and apparatus for instruction pointer storage element configuration in a simultaneous multithreaded processorINTEL CORP·Filed 2006·Application pending·0 cites
- 3247US2011161585A1Processing non-ownership load requests hitting modified line in cache of a different processorKOTTAPALLI SAILESH·Filed 2009·Application pending·0 cites
- 3346US6721873B2Method and apparatus for improving dispersal performance in a processor through the use of no-op portsINTEL CORP·Filed 2000·Granted Apr 13, 2004·1 cites·17 claims
- 3446US2006101208A1Method and apparatus for handling non-temporal memory accesses in a cacheINTEL CORP·Filed 2004·Application pending·0 cites
- 3545US2005114632A1Method and apparatus for data speculation in an out-of-order processorINTEL CORP·Filed 2003·Application pending·0 cites
- 3644US2005066151A1Method and apparatus for handling predicated instructions in an out-of-order processorFiled 2003·Application pending·0 cites
- 3741US2002188805A1Mechanism for implementing cache line fillsFiled 2001·Application pending·0 cites
- 3841US2014281270A1Mechanism to improve input/output write bandwidth in scalable systems utilizing directory based coherecyNEEFS HENK G·Filed 2013·Application pending·0 cites
- 3939US10204049B2Value of forward state by increasing local caching agent forwardingGEETHA VEDARAMAN·Filed 2012·Granted Feb 12, 2019·0 cites·20 claims
- 4039US8495091B2Dynamically routing data responses directly to requesting processor coreBAUM ALLEN J·Filed 2011·Granted Jul 23, 2013·0 cites·20 claims
- 4138US2002087833A1Method and apparatus for distributed processor dispersal logicFiled 2000·Application pending·0 cites
- 4238US2013007376A1Opportunistic snoop broadcast (osb) in directory enabled home snoopy systemsKOTTAPALLI SAILESH·Filed 2011·Application pending·0 cites
- 4337US2006156177A1Method and apparatus for recovering from soft errors in register filesKOTTAPALLI SAILESH·Filed 2004·Application pending·0 cites
- 4431US2006143374A1Pipelined look-up in a content addressable memoryKOTTAPALLI SAILESH·Filed 2004·Application pending·0 cites
- 4530US2003084389A1Method and apparatus for flexible memory for defect toleranceFiled 2001·Application pending·0 cites
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