Inventor · disambiguated record
Cho Moon
Also filed as: MOON CHO · MOON CHO W · MOON CHO WOO
9 granted patents·89 citations·filing 2002–2021
87Inventor score
Technology areasG06F
Files withCADENCE DESIGN SYSTEMS INC3SRIPADA SUBRAMANYAM3SINGHAL SONIA1SYNOPSYS INC1TELA INNOVATIONS INC1
Top patents by PatentIndex Score
9 records- 0182US7356451B2Assertion handling for timing model extractionCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Apr 8, 2008·30 cites·61 claims
- 0282US6928630B2Timing model extraction by timing graph reductionCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Aug 9, 2005·31 cites·53 claims
- 0375US8627262B2Automatic generation of merged mode constraints for electronic circuitsSRIPADA SUBRAMANYAM·Filed 2010·Granted Jan 7, 2014·5 cites·17 claims
- 0473US8261221B2Comparing timing constraints of circuitsSINGHAL SONIA·Filed 2010·Granted Sep 4, 2012·8 cites·21 claims
- 0571US8607186B2Automatic verification of merged mode constraints for electronic circuitsSRIPADA SUBRAMANYAM·Filed 2011·Granted Dec 10, 2013·4 cites·17 claims
- 0669US8701074B2Automatic reduction of modes of electronic circuits for timing analysisSRIPADA SUBRAMANYAM·Filed 2011·Granted Apr 15, 2014·3 cites·24 claims
- 0765US7823098B1Method of designing a digital circuit by correlating different static timing analyzersTELA INNOVATIONS INC·Filed 2006·Granted Oct 26, 2010·4 cites·7 claims
- 0853US7418684B1Systems, methods, and apparatus to perform static timing analysis and optimization for multi-mode clock circuit networksCADENCE DESIGN SYSTEMS INC·Filed 2004·Granted Aug 26, 2008·4 cites·44 claims
- 0950US12175181B1Timing-aware surgical optimization for engineering change order in chip designSYNOPSYS INC·Filed 2021·Granted Dec 24, 2024·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →