Inventor · disambiguated record
James Steele
Also filed as: STEELE JAMES · STEELE JAMES C · STEELE JAMES CRAWFORD
13 granted patents·4 pending applications·414 citations·filing 1975–2023
92Inventor score
Files withVLSI TECHNOLOGY INC5KONINKL PHILIPS ELECTRONICS NV3DIALOG SEMICONDUCTOR UK LTD2RENESAS DESIGN UK LTD2STEELE JAMES C2
Top patents by PatentIndex Score
17 records- 0194US6385749B1Method and arrangement for controlling multiple test access port control modulesKONINKL PHILIPS ELECTRONICS NV·Filed 1999·Granted May 7, 2002·127 cites·28 claims
- 0291US6311302B1Method and arrangement for hierarchical control of multiple test access port control modulesPHILIPS SEMICONDUCTOR INC·Filed 1999·Granted Oct 30, 2001·98 cites·20 claims
- 0384US6334198B1Method and arrangement for controlling multiply-activated test access port control modulesKONINKL PHILIPS ELECTRONICS NV·Filed 1999·Granted Dec 25, 2001·56 cites·20 claims
- 0468US10998818B2Asynchronous dropout transition for multi-level and single-level buck convertersDIALOG SEMICONDUCTOR UK LTD·Filed 2019·Granted May 4, 2021·1 cites·20 claims
- 0563US6782466B1Arrangement and method for accessing data in a virtual memory arrangementKONINKL PHILIPS ELECTRONICS NV·Filed 1999·Granted Aug 24, 2004·47 cites·2 claims
- 0659US5793992AMethod and apparatus for arbitrating access to main memory of a computer systemVLSI TECHNOLOGY INC·Filed 1996·Granted Aug 11, 1998·39 cites·23 claims
- 0758US12199503B2Driver for switched mode power supplyRENESAS DESIGN UK LTD·Filed 2022·Granted Jan 14, 2025·0 cites·18 claims
- 0858US11539294B2Multi-level power converter with light load flying capacitor voltage regulationDIALOG SEMICONDUCTOR UK LTD·Filed 2018·Granted Dec 27, 2022·1 cites·22 claims
- 0946US5815675AMethod and apparatus for direct access to main memory by an I/O busVLSI TECHNOLOGY INC·Filed 1996·Granted Sep 29, 1998·22 cites·17 claims
- 1046US2008043931A1Calibration system for telephoneACOUSTIC TECH INC·Filed 2006·Application pending·0 cites
- 1142US2024362035A1Asynchronous finite state machine circuitRENESAS DESIGN UK LTD·Filed 2023·Application pending·0 cites
- 1238US2014081627A1Method for optimization of multiple psychoacoustic effectsROCHA ED·Filed 2012·Application pending·0 cites
- 1336US3986461ACarrelSTEELE JAMES C·Filed 1975·Granted Oct 19, 1976·10 cites·10 claims
- 1434US2014059101A1Optimized method of biquad infinite-impulse response calculationSTEELE JAMES C·Filed 2012·Application pending·0 cites
- 1533US5664213AInput/output (I/O) holdoff mechanism for use in a system where I/O device inputs are fed through a latency introducing busVLSI TECHNOLOGY INC·Filed 1995·Granted Sep 2, 1997·6 cites·21 claims
- 1629US5732226AApparatus for granting either a CPU data bus or a memory data bus or a memory data bus access to a PCI busVLSI TECHNOLOGY INC·Filed 1996·Granted Mar 24, 1998·3 cites·7 claims
- 1725US5799178ASystem and method for starting and maintaining a central processing unit (CPU) clock using clock division emulation (CDE) during break eventsVLSI TECHNOLOGY INC·Filed 1996·Granted Aug 25, 1998·4 cites·4 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →