Inventor · disambiguated record
Donald B. Alpert
Also filed as: ALPERT DONALD · ALPERT DONALD B
35 granted patents·1 pending application·2,831 citations·filing 1987–2007
99Inventor score
Top patents by PatentIndex Score
36 records- 0198US7389403B1Adaptive computing ensemble microprocessor architectureSUN MICROSYSTEMS INC·Filed 2006·Granted Jun 17, 2008·155 cites·24 claims
- 0297US7802073B1Virtual core managementORACLE AMERICA INC·Filed 2007·Granted Sep 21, 2010·132 cites·18 claims
- 0395US5638525AProcessor capable of executing programs that contain RISC and CISC instructionsINTEL CORP·Filed 1995·Granted Jun 10, 1997·266 cites·19 claims
- 0495US5617554APhysical address size selection and page size selection in an address translatorINTEL CORP·Filed 1994·Granted Apr 1, 1997·198 cites·28 claims
- 0595US5559986AInterleaved cache for multiple accesses per clock cycle in a microprocessorINTEL CORP·Filed 1994·Granted Sep 24, 1996·131 cites·23 claims
- 0694US6408386B1Method and apparatus for providing event handling functionality in a computer systemINTEL CORP·Filed 2001·Granted Jun 18, 2002·90 cites·15 claims
- 0792US5479652AMicroprocessor with an external command mode for diagnosis and debuggingINTEL CORP·Filed 1994·Granted Dec 26, 1995·220 cites·36 claims
- 0891US5675825AApparatus and method for identifying a computer microprocessorINTEL CORP·Filed 1995·Granted Oct 7, 1997·132 cites·21 claims
- 0987US5657253AApparatus for monitoring the performance of a microprocessorINTEL CORP·Filed 1992·Granted Aug 12, 1997·121 cites·23 claims
- 1086US5442756ABranch prediction and resolution apparatus for a superscalar computer processorINTEL CORP·Filed 1992·Granted Aug 15, 1995·101 cites·15 claims
- 1185US5740413AMethod and apparatus for providing address breakpoints, branch breakpoints, and single steppingINTEL CORP·Filed 1997·Granted Apr 14, 1998·120 cites·17 claims
- 1284US5774686AMethod and apparatus for providing two system architectures in a processorINTEL CORP·Filed 1995·Granted Jun 30, 1998·104 cites·66 claims
- 1384US5659679AMethod and apparatus for providing breakpoints on taken jumps and for providing software profiling in a computer systemINTEL CORP·Filed 1995·Granted Aug 19, 1997·118 cites·15 claims
- 1484US5621886AMethod and apparatus for providing efficient software debuggingINTEL CORP·Filed 1995·Granted Apr 15, 1997·116 cites·34 claims
- 1584US5606676ABranch prediction and resolution apparatus for a superscalar computer processorINTEL CORP·Filed 1995·Granted Feb 25, 1997·103 cites·13 claims
- 1676US5692167AMethod for verifying the correct processing of pipelined instructions including branch instructions and self-modifying code in a microprocessorINTEL CORP·Filed 1996·Granted Nov 25, 1997·74 cites·15 claims
- 1776US5249286ASelectively locking memory locations within a microprocessor's on-chip cacheNAT SEMICONDUCTOR CORP·Filed 1992·Granted Sep 28, 1993·70 cites·22 claims
- 1874US4802085AApparatus and method for detecting and handling memory-mapped I/O by a pipelined microprocessorNAT SEMICONDUCTOR CORP·Filed 1987·Granted Jan 31, 1989·60 cites·5 claims
- 1973US5729724AAdaptive 128-bit floating point load and store operations for quadruple precision compatibilityINTEL CORP·Filed 1995·Granted Mar 17, 1998·68 cites·20 claims
- 2072US5671435ATechnique for software to identify features implemented in a processorINTEL CORP·Filed 1995·Granted Sep 23, 1997·43 cites·20 claims
- 2171US5802605APhysical address size selection and page size selection in an address translatorINTEL CORP·Filed 1996·Granted Sep 1, 1998·52 cites·18 claims
- 2270US6219774B1Address translation with/bypassing intermediate segmentation translation to accommodate two different instruction set architectureINTEL CORP·Filed 1998·Granted Apr 17, 2001·48 cites·14 claims
- 2366US6584558B2Article for providing event handling functionality in a processor supporting different instruction setsINTEL CORP·Filed 2002·Granted Jun 24, 2003·10 cites·15 claims
- 2465US5958037AApparatus and method for identifying the features and the origin of a computer microprocessorINTEL CORP·Filed 1993·Granted Sep 28, 1999·31 cites·30 claims
- 2562US5991874AConditional move using a compare instruction generating a condition fieldINTEL CORP·Filed 1996·Granted Nov 23, 1999·41 cites·20 claims
- 2661US5790834AApparatus and method using an ID instruction to identify a computer microprocessorINTEL CORP·Filed 1992·Granted Aug 4, 1998·23 cites·26 claims
- 2760US5475824AMicroprocessor with apparatus for parallel execution of instructionsINTEL CORP·Filed 1995·Granted Dec 12, 1995·41 cites·14 claims
- 2856US5263153AMonitoring control flow in a microprocessorNAT SEMICONDUCTOR CORP·Filed 1990·Granted Nov 16, 1993·30 cites·16 claims
- 2954US7010671B2Computer system and method for executing interrupt instructions in two operating modesINTEL CORP·Filed 2002·Granted Mar 7, 2006·2 cites·22 claims
- 3051US6385718B1Computer system and method for executing interrupt instructions in operating modesINTEL CORP·Filed 1997·Granted May 7, 2002·19 cites·14 claims
- 3151US6052801AMethod and apparatus for providing breakpoints on a selectable address rangeINTEL CORP·Filed 1995·Granted Apr 18, 2000·23 cites·22 claims
- 3251US5669011APartially decoded instruction cacheNAT SEMICONDUCTOR CORP·Filed 1996·Granted Sep 16, 1997·24 cites·16 claims
- 3351US5481751AApparatus and method for storing partially-decoded instructions in the instruction cache of a CPU having multiple execution unitsNAT SEMICONDUCTOR CORP·Filed 1994·Granted Jan 2, 1996·22 cites·2 claims
- 3449US5416913AMethod and apparatus for dependency checking in a multi-pipelined microprocessorINTEL CORP·Filed 1994·Granted May 16, 1995·22 cites·3 claims
- 3549US2005091480A1Computer system and method for executing interrupt instructions in operating modesFiled 2004·Application pending·0 cites
- 3648US5764959AAdaptive 128-bit floating point load and store instructions for quad-precision compatibilityINTEL CORP·Filed 1995·Granted Jun 9, 1998·21 cites·15 claims
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