Inventor · disambiguated record
Brian W. Curran
Also filed as: CURRAN BRIAN · CURRAN BRIAN W · CURRAN BRIAN WILLIAM
50 granted patents·5 pending applications·540 citations·filing 1984–2022
98Inventor score
Top patents by PatentIndex Score
55 records- 0197US11138010B1Loop management in multi-processor dataflow architectureIBM·Filed 2020·Granted Oct 5, 2021·7 cites·20 claims
- 0295US8495341B2Instruction length based cracking for instruction of variable length storage operandsBUSABA FADI·Filed 2010·Granted Jul 23, 2013·47 cites·20 claims
- 0393US8521992B2Predicting and avoiding operand-store-compare hazards in out-of-order microprocessorsALEXANDER GREGORY W·Filed 2010·Granted Aug 27, 2013·21 cites·24 claims
- 0489US5568075ATiming signal generatorIBM·Filed 1995·Granted Oct 22, 1996·69 cites·13 claims
- 0583US8645669B2Cracking destructively overlapping operands in variable length instructionsALEXANDER KHARY J·Filed 2010·Granted Feb 4, 2014·8 cites·24 claims
- 0682US9135005B2History and alignment based cracking for store multiple instructions for optimizing operand store compare penaltiesALEXANDER KHARY J·Filed 2010·Granted Sep 15, 2015·7 cites·20 claims
- 0782US7237094B2Instruction group formation and mechanism for SMT dispatchIBM·Filed 2004·Granted Jun 26, 2007·33 cites·21 claims
- 0881US9619385B2Single thread cache miss rate estimationIBM·Filed 2015·Granted Apr 11, 2017·3 cites·13 claims
- 0979US9430235B2Predicting and avoiding operand-store-compare hazards in out-of-order microprocessorsIBM·Filed 2013·Granted Aug 30, 2016·4 cites·20 claims
- 1079US8468325B2Predicting and avoiding operand-store-compare hazards in out-of-order microprocessorsALEXANDER GREGORY W·Filed 2009·Granted Jun 18, 2013·9 cites·19 claims
- 1174US6426661B1Clock distribution with constant delay clock buffer circuitIBM·Filed 2001·Granted Jul 30, 2002·17 cites·8 claims
- 1270US10838868B2Programmable data delivery by load and store agents on a processing chip interfacing with on-chip memory components and directing data to external memory componentsIBM·Filed 2019·Granted Nov 17, 2020·1 cites·21 claims
- 1370US8464030B2Instruction cracking and issue shortening based on instruction base fields, index fields, operand fields, and various other instruction text bitsBUSABA FADI·Filed 2010·Granted Jun 11, 2013·3 cites·19 claims
- 1470US6661262B1Frequency doubling two-phase clock generation circuitIBM·Filed 2002·Granted Dec 9, 2003·14 cites·9 claims
- 1569US9389865B1Accelerated execution of target of execute instructionIBM·Filed 2015·Granted Jul 12, 2016·1 cites·1 claims
- 1668US7537018B1Method and apparatus for controlling partial vapor pressure in a sorption analyzerWATERS INVESTMENTS LTD·Filed 2006·Granted May 26, 2009·7 cites·20 claims
- 1767US5032985AMultiprocessor system with memory fetch buffer invoked during cross-interrogationIBM·Filed 1988·Granted Jul 16, 1991·45 cites·15 claims
- 1865US9575529B2Voltage droop reduction in a processorIBM·Filed 2015·Granted Feb 21, 2017·1 cites·17 claims
- 1965US9104399B2Dual issuing of complex instruction set instructionsBUSABA FADI·Filed 2009·Granted Aug 11, 2015·3 cites·19 claims
- 2064US11379228B2Microprocessor including an efficiency logic unitIBM·Filed 2019·Granted Jul 5, 2022·0 cites·6 claims
- 2163US7904697B2Load register instruction short circuiting methodIBM·Filed 2008·Granted Mar 8, 2011·2 cites·17 claims
- 2263US5278967ASystem for providing gapless data transfer from page-mode dynamic random access memoriesIBM·Filed 1990·Granted Jan 11, 1994·39 cites·14 claims
- 2362US5554946ATiming signal generatorIBM·Filed 1994·Granted Sep 10, 1996·14 cites·2 claims
- 2460US10540183B2Accelerated execution of execute instruction targetIBM·Filed 2017·Granted Jan 21, 2020·0 cites·16 claims
- 2560US6104212ACommon domino circuit evaluation deviceIBM·Filed 1998·Granted Aug 15, 2000·16 cites·17 claims
- 2660US5939915ANoise-immune pass gate latchIBM·Filed 1997·Granted Aug 17, 1999·16 cites·15 claims
- 2759US7676779B2Logic block timing estimation using conesizeIBM·Filed 2007·Granted Mar 9, 2010·2 cites·16 claims
- 2859US5572736AMethod and apparatus for reducing bus noise and power consumptionIBM·Filed 1995·Granted Nov 5, 1996·32 cites·8 claims
- 2958US10514911B2Structure for microprocessor including arithmetic logic units and an efficiency logic unitIBM·Filed 2014·Granted Dec 24, 2019·0 cites·7 claims
- 3058USD292998SGames sheetCURRAN BRIAN·Filed 1984·Granted Dec 1, 1987·6 cites·1 claims
- 3157US2015051957A1Measuring customer experience valueORACLE INT CORP·Filed 2013·Application pending·0 cites
- 3254US10503503B2Generating design structure for microprocessor with arithmetic logic units and an efficiency logic unitIBM·Filed 2015·Granted Dec 10, 2019·0 cites·6 claims
- 3354US9875107B2Accelerated execution of execute instruction targetIBM·Filed 2015·Granted Jan 23, 2018·0 cites·16 claims
- 3453US6882205B2Low power overdriven pass gate latchIBM·Filed 2002·Granted Apr 19, 2005·3 cites·10 claims
- 3552US7991816B2Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution unitsIBM·Filed 2008·Granted Aug 2, 2011·0 cites·10 claims
- 3651US9626293B2Single-thread cache miss rate estimationIBM·Filed 2015·Granted Apr 18, 2017·0 cites·7 claims
- 3751US6768365B2Low power reduced voltage swing latchIBM·Filed 2002·Granted Jul 27, 2004·2 cites·5 claims
- 3851US5771369AMemory row redriveIBM·Filed 1995·Granted Jun 23, 1998·13 cites·21 claims
- 3951US2016239305A1Branch target buffer column predictorIBM·Filed 2016·Application pending·0 cites
- 4050US10205623B2Custom event and attribute generation for use in website traffic data collectionERROR BRETT·Filed 2003·Granted Feb 12, 2019·4 cites·18 claims
- 4150US6966046B2CMOS tapered gate and synthesis methodIBM·Filed 2001·Granted Nov 15, 2005·3 cites·8 claims
- 4249US5765207ARecursive hardware state machineIBM·Filed 1996·Granted Jun 9, 1998·22 cites·2 claims
- 4349US5574921AMethod and apparatus for reducing bus noise and power consumptionIBM·Filed 1995·Granted Nov 12, 1996·18 cites·13 claims
- 4448US2016239309A1Branch target buffer column predictorIBM·Filed 2015·Application pending·0 cites
- 4546US7509365B2Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution unitsIBM·Filed 2005·Granted Mar 24, 2009·0 cites·1 claims
- 4646US6657471B1High performance, low power differential latchIBM·Filed 2002·Granted Dec 2, 2003·3 cites·7 claims
- 4745US11223703B2Instruction initialization in a dataflow architectureIBM·Filed 2019·Granted Jan 11, 2022·0 cites·14 claims
- 4845US5428762AExpandable memory having plural memory cards for distributively storing system dataIBM·Filed 1992·Granted Jun 27, 1995·16 cites·7 claims
- 4945USD292999SGames sheetCURRAN BRIAN·Filed 1984·Granted Dec 1, 1987·3 cites·1 claims
- 5045US2023344667A1Single-producer-multiple consumers synchronization and multicast data transferIBM·Filed 2022·Application pending·0 cites
Showing the top 50 of 55 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Brian W. Curran files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →