Inventor · disambiguated record
James Yamaguchi
Also filed as: YAMAGUCHI JAMES · YAMAGUCHI JAMES S · YAMAGUCHI JAMES SATSUO · YAMAGUCHI JAMES SATSUO UJIIE
20 granted patents·9 pending applications·738 citations·filing 1989–2023
96Inventor score
Top patents by PatentIndex Score
29 records- 0196US7335576B2Method for precision integrated circuit die singulation using differential etch ratesIRVINE SENSORS CORP·Filed 2005·Granted Feb 26, 2008·61 cites·14 claims
- 0292US7127807B2Process of manufacturing multilayer modulesIRVINE SENSORS CORP·Filed 2003·Granted Oct 31, 2006·69 cites·5 claims
- 0391US6784547B2Stackable layers containing encapsulated integrated circuit chips with one or more overlying interconnect layersIRVINE SENSORS CORP·Filed 2002·Granted Aug 31, 2004·46 cites·16 claims
- 0491US6117704AStackable layers containing encapsulated chipsIRVINE SENSORS CORP·Filed 1999·Granted Sep 12, 2000·137 cites·15 claims
- 0591US5953588AStackable layers containing encapsulated IC chipsIRVINE SENSORS CORP·Filed 1996·Granted Sep 14, 1999·128 cites·14 claims
- 0690US6072234AStack of equal layer neo-chips containing encapsulated IC chips of different sizesIRVINE SENSORS CORP·Filed 1999·Granted Jun 6, 2000·105 cites·33 claims
- 0788US6560109B2Stack of multilayer modules with heat-focusing metal layerIRVINE SENSORS CORP·Filed 2001·Granted May 6, 2003·44 cites·10 claims
- 0883US6734370B2Multilayer modules with flexible substratesIRVINE SENSORS CORP·Filed 2001·Granted May 11, 2004·32 cites·13 claims
- 0980US7786562B2Stackable semiconductor chip layer comprising prefabricated trench interconnect viasOZGUZ VOLKAN·Filed 2005·Granted Aug 31, 2010·11 cites·34 claims
- 1080US6717061B2Stacking of multilayer modulesIRVINE SENSORS CORP·Filed 2001·Granted Apr 6, 2004·30 cites·3 claims
- 1173US5123164AHermetic organic/inorganic interconnection substrate for hybrid circuit manufactureROCKWELL INTERNATIONAL CORP·Filed 1990·Granted Jun 23, 1992·47 cites·11 claims
- 1270US6797537B2Method of making stackable layers containing encapsulated integrated circuit chips with one or more overlaying interconnect layersIRVINE SENSORS CORP·Filed 2001·Granted Sep 28, 2004·10 cites·21 claims
- 1363US8637985B2Anti-tamper wrapper interconnect method and a deviceBINDRUP RANDY·Filed 2012·Granted Jan 28, 2014·2 cites·5 claims
- 1463USRE43877EMethod for precision integrated circuit die singulation using differential etch ratesLUDWIG DAVID·Filed 2010·Granted Dec 25, 2012·1 cites·42 claims
- 1560US7239012B2Three-dimensional module comprised of layers containing IC chips with overlying interconnect layersIRVINE SENSORS CORP·Filed 2004·Granted Jul 3, 2007·5 cites·2 claims
- 1659US9431275B2Wire bond through-via structure and methodBINDRUP RANDY·Filed 2011·Granted Aug 30, 2016·1 cites·12 claims
- 1758US2024395934A1Semiconductor devices for use in high-pressure environmentsBOEING CO·Filed 2023·Application pending·0 cites
- 1848US9741680B1Wire bond through-via structure and methodPFG IP LLC·Filed 2016·Granted Aug 22, 2017·0 cites·1 claims
- 1944US8637140B2Method for defining an electrically conductive metal structure on a three-dimensional element and a device made from the methodYAMAGUCHI JAMES·Filed 2011·Granted Jan 28, 2014·0 cites·5 claims
- 2041US2010291735A1Stackable semiconductor chip layer comprising prefabricated trench interconnect viasOZGUZ VOLKAN·Filed 2010·Application pending·0 cites
- 2141US2020006367A13D-Stacked Module with Unlimited Scalable Memory Architecture for Very High Bandwidth and Very High Capacity Data Processing DevicesIRVINE SENSORS CORP·Filed 2019·Application pending·0 cites
- 2240US5030499AHermetic organic/inorganic interconnection substrate for hybrid circuit manufactureROCKWELL INTERNATIONAL CORP·Filed 1989·Granted Jul 9, 1991·9 cites·6 claims
- 2338US2011227603A1Secure Anti-Tamper Integrated Layer Security Device Comprising Nano-StructuresIRVINE SENSORS CORP·Filed 2011·Application pending·0 cites
- 2437US2003049889A1Method of manufacturing multilayer modulesFiled 2001·Application pending·0 cites
- 2537US2011031982A1Tamper-resistant electronic circuit and module incorporating electrically conductive nano-structuresIRVINE SENSORS CORP·Filed 2010·Application pending·0 cites
- 2635US2004113222A1Stacked microelectronic module with vertical interconnect viasOZGUZ VOLKAN H·Filed 2003·Application pending·0 cites
- 2735US2012069528A1Method for Control of Solder Collapse in Stacked Microelectronic StructureBINDRUP RANDY·Filed 2011·Application pending·0 cites
- 2832US8609473B2Method for fabricating a neo-layer using stud bumped bare dieLIEU PETER·Filed 2011·Granted Dec 17, 2013·0 cites·1 claims
- 2931US2012211886A1Method for Fabricating a Small Footprint Chip-Scale Package and a Device Made from the MethodLIEU PETER·Filed 2012·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when James Yamaguchi files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →