Inventor · disambiguated record
Talal K. Jaber
Also filed as: JABER TALAL · JABER TALAL K · JABER TALAL KAMEL
11 granted patents·1 pending application·414 citations·filing 1995–2009
92Inventor score
Top patents by PatentIndex Score
12 records- 0189US5614838AReduced power apparatus and method for testing high speed componentsIBM·Filed 1995·Granted Mar 25, 1997·91 cites·9 claims
- 0288US6815977B2Scan cell systems and methodsINTEL CORP·Filed 2002·Granted Nov 9, 2004·55 cites·20 claims
- 0385US6055658AApparatus and method for testing high speed components using low speed test apparatusIBM·Filed 1995·Granted Apr 25, 2000·65 cites·5 claims
- 0482US6028983AApparatus and methods for testing a microprocessor chip using dedicated scan stringsIBM·Filed 1996·Granted Feb 22, 2000·114 cites·10 claims
- 0571US7028239B2Microprocessor on-chip testing architecture and implementationINTEL CORP·Filed 2000·Granted Apr 11, 2006·16 cites·18 claims
- 0670US7437634B2Test scan cellsINTEL CORP·Filed 2003·Granted Oct 14, 2008·16 cites·25 claims
- 0768US5748012AMethodology to test pulsed logic circuits in pseudo-static modeIBM·Filed 1996·Granted May 5, 1998·23 cites·15 claims
- 0867US5926487AHigh performance registers for pulsed logicIBM·Filed 1996·Granted Jul 20, 1999·31 cites·46 claims
- 0948US7216274B2Flexible scan architectureINTEL CORP·Filed 2003·Granted May 8, 2007·3 cites·38 claims
- 1043US7734972B2Common test logic for multiple operation modesINTEL CORP·Filed 2008·Granted Jun 8, 2010·0 cites·15 claims
- 1139US8321730B2Scan architecture and design methodology yielding significant reduction in scan area and power overheadJABER TALAL K·Filed 2009·Granted Nov 27, 2012·0 cites·20 claims
- 1236US2007168767A1Flexible scan architectureJABER TALAL K·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →