Inventor · disambiguated record
Russell W. Dyer
Also filed as: DYER RUSSELL W
9 granted patents·1 pending application·370 citations·filing 1996–2003
90Inventor score
Top patents by PatentIndex Score
10 records- 0191US6629220B1Method and apparatus for dynamic arbitration between a first queue and a second queue based on a high priority transaction typeINTEL CORP·Filed 1999·Granted Sep 30, 2003·201 cites·29 claims
- 0279US6433785B1Method and apparatus for improving processor to graphics device throughputINTEL CORP·Filed 1999·Granted Aug 13, 2002·91 cites·17 claims
- 0366US6665794B2Data reordering mechanism for data transfer in computer systemsINTEL CORP·Filed 2002·Granted Dec 16, 2003·9 cites·17 claims
- 0452US7058736B2Reordering of burst data transfers across a host bridgeINTEL CORP·Filed 2002·Granted Jun 6, 2006·3 cites·18 claims
- 0551US6457121B1Method and apparatus for reordering data in X86 orderingINTEL CORP·Filed 1999·Granted Sep 24, 2002·18 cites·25 claims
- 0650US7089367B1Reducing memory access latencies from a bus using pre-fetching and cachingINTEL CORP·Filed 1999·Granted Aug 8, 2006·14 cites·21 claims
- 0746US2004095355A1Computer chipsets having data reordering mechanismINTEL CORP A CALIFORNIA CORP·Filed 2003·Application pending·0 cites
- 0843US6505259B1Reordering of burst data transfers across a host bridgeINTEL CORP·Filed 1999·Granted Jan 7, 2003·15 cites·14 claims
- 0940US5696768AMethod and apparatus for data storage array trackingINTEL CORP·Filed 1996·Granted Dec 9, 1997·12 cites·21 claims
- 1034US6593931B1Method and apparatus for improving system memory bandwidth utilization during graphics translational lookaside buffer cache miss fetch cyclesINTEL CORP·Filed 1999·Granted Jul 15, 2003·7 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →