Inventor · disambiguated record
Jamison D. Collins
Also filed as: COLLINS JAMISON · COLLINS JAMISON D
25 granted patents·2 pending applications·275 citations·filing 2001–2018
95Inventor score
Technology areasG06F
Top patents by PatentIndex Score
27 records- 0194US8296743B2Compiler and runtime for heterogeneous multiprocessor systemsLINDERMAN MICHAEL D·Filed 2007·Granted Oct 23, 2012·84 cites·25 claims
- 0293US10585667B2Method and system to provide user-level multithreadingINTEL CORP·Filed 2018·Granted Mar 10, 2020·7 cites·18 claims
- 0389US7941791B2Programming environment for heterogeneous processor resource integrationWANG PERRY·Filed 2007·Granted May 10, 2011·31 cites·12 claims
- 0489US7587584B2Mechanism to exploit synchronization overhead to improve multithreaded performanceINTEL CORP·Filed 2005·Granted Sep 8, 2009·31 cites·25 claims
- 0587US7768518B2Enabling multiple instruction stream/multiple data stream extensions on microprocessorsINTEL CORP·Filed 2006·Granted Aug 3, 2010·19 cites·15 claims
- 0686US8719547B2Providing hardware support for shared virtual memory between local and remote physical memoryCHINYA GAUTHAM N·Filed 2009·Granted May 6, 2014·20 cites·29 claims
- 0785US6928645B2Software-based speculative pre-computation and multithreadingINTEL CORP·Filed 2001·Granted Aug 9, 2005·48 cites·16 claims
- 0879US7904696B2Communication paths for enabling inter-sequencer communication following lock competition and accelerator registrationINTEL CORP·Filed 2007·Granted Mar 8, 2011·7 cites·16 claims
- 0978US9003164B2Providing hardware support for shared virtual memory between local and remote physical memoryINTEL CORP·Filed 2014·Granted Apr 7, 2015·4 cites·20 claims
- 1075US10216516B2Fused adjacent memory storesINTEL CORP·Filed 2016·Granted Feb 26, 2019·2 cites·24 claims
- 1172US8843728B2Processor for enabling inter-sequencer communication following lock competition and accelerator registrationINTEL CORP·Filed 2012·Granted Sep 23, 2014·2 cites·19 claims
- 1267US9904546B2Instruction and logic for predication and implicit destinationINTEL CORP·Filed 2015·Granted Feb 27, 2018·1 cites·20 claims
- 1366US7051193B2Register rotation prediction and precomputationINTEL CORP·Filed 2001·Granted May 23, 2006·12 cites·34 claims
- 1465US8074274B2User-level privilege managementWANG HONG·Filed 2006·Granted Dec 6, 2011·3 cites·23 claims
- 1564US10635438B2Method and system to provide user-level multithreadingINTEL CORP·Filed 2018·Granted Apr 28, 2020·0 cites·23 claims
- 1664US10628153B2Method and system to provide user-level multithreadingINTEL CORP·Filed 2018·Granted Apr 21, 2020·0 cites·17 claims
- 1764US10613858B2Method and system to provide user-level multithreadingINTEL CORP·Filed 2018·Granted Apr 7, 2020·0 cites·21 claims
- 1864US9823938B2Providing deterministic, reproducible, and random sampling in a processorINTEL CORP·Filed 2015·Granted Nov 21, 2017·1 cites·17 claims
- 1959US9952859B2Method and system to provide user-level multithreadingINTEL CORP·Filed 2016·Granted Apr 24, 2018·0 cites·15 claims
- 2058US10884735B2Instruction and logic for predication and implicit destinationINTEL CORP·Filed 2018·Granted Jan 5, 2021·0 cites·20 claims
- 2155US9189230B2Method and system to provide concurrent user-level, non-privileged shared resource thread creation and executionGROCHOWSKI EDWARD T·Filed 2004·Granted Nov 17, 2015·3 cites·43 claims
- 2251US8380963B2Apparatus and method for enabling inter-sequencer communication following lock competition and accelerator registrationINTEL CORP·Filed 2011·Granted Feb 19, 2013·0 cites·15 claims
- 2347US2016179538A1Method and apparatus for implementing and maintaining a stack of predicate values with stack synchronization instructions in an out of order hardware software co-designed processorINTEL CORP·Filed 2014·Application pending·0 cites
- 2444US2016179549A1Instruction and Logic for Loop Stream DetectionINTEL CORP·Filed 2014·Application pending·0 cites
- 2540US10635465B2Apparatuses and methods to prevent execution of a modified instructionINTEL CORP·Filed 2015·Granted Apr 28, 2020·0 cites·16 claims
- 2639US10346170B2Performing partial register write operations in a processorINTEL CORP·Filed 2015·Granted Jul 9, 2019·0 cites·18 claims
- 2739US8621153B2Microcode refactoring and cachingCOLLINS JAMISON D·Filed 2010·Granted Dec 31, 2013·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →