Inventor · disambiguated record
Hun-Hsien Chang
Also filed as: CHANG HUN-HSIEN
17 granted patents·1 pending application·1,584 citations·filing 1995–2003
96Inventor score
Top patents by PatentIndex Score
18 records- 0197US6249410B1ESD protection circuit without overstress gate-driven effectTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Jun 19, 2001·222 cites·38 claims
- 0297US6144542AESD bus lines in CMOS IC's for whole-chip ESD protectionTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Nov 7, 2000·215 cites·37 claims
- 0395US6765771B2SCR devices with deep-N-well structure for on-chip ESD protection circuitsTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Jul 20, 2004·122 cites·26 claims
- 0495US6008684ACMOS output buffer with CMOS-controlled lateral SCR devicesIND TECH RES INST·Filed 1996·Granted Dec 28, 1999·126 cites·16 claims
- 0595US5576557AComplementary LVTSCR ESD protection circuit for sub-micron CMOS integrated circuitsUNITED MICROELECTRONICS CORP·Filed 1995·Granted Nov 19, 1996·154 cites·14 claims
- 0694US6671153B1Low-leakage diode string for use in the power-rail ESD clamp circuitsTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Dec 30, 2003·102 cites·16 claims
- 0794US6566715B1Substrate-triggered technique for on-chip ESD protection circuitTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted May 20, 2003·89 cites·30 claims
- 0893US6011681AWhole-chip ESD protection for CMOS ICs using bi-directional SCRsTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Jan 4, 2000·114 cites·16 claims
- 0993US5959820ACascode LVTSCR and ESD protection circuitTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Sep 28, 1999·117 cites·56 claims
- 1090US6514839B1ESD implantation method in deep-submicron CMOS technology for high-voltage-tolerant applications with light-doping concentrationsTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Feb 4, 2003·46 cites·10 claims
- 1188US6576958B2ESD protection networks with NMOS-bound or PMOS-bound diode structures in a shallow-trench-isolation (STI) CMOS processTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Jun 10, 2003·46 cites·58 claims
- 1287US6838734B2ESD implantation in deep-submicron CMOS technology for high-voltage-tolerant applicationsTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Jan 4, 2005·35 cites·12 claims
- 1386US6002568AESD protection scheme for mixed-voltage CMOS integrated circuitsTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Dec 14, 1999·66 cites·24 claims
- 1485US6885529B2CDM ESD protection design using deep N-well structureTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Apr 26, 2005·38 cites·22 claims
- 1585US6388850B1Gate-coupled ESD protection circuit without transient leakageTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted May 14, 2002·68 cites·21 claims
- 1665US7054122B2VDDCORE to VSS ESD clamp made of core deviceTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted May 30, 2006·12 cites·5 claims
- 1764US6444404B1Method of fabricating ESD protection device by using the same photolithographic mask for both the ESD implantation and the silicide blocking regionsTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Sep 3, 2002·12 cites·21 claims
- 1834US2002130390A1ESD protection circuit with very low input capacitance for high-frequency I/O portsFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →