Inventor · disambiguated record
Arthur J. O'Neill
Also filed as: O'NEILL ARTHUR · O'NEILL ARTHUR J · O'NEILL ARTHUR J JR · O'NEILL JR ARTHUR J
68 granted patents·4 pending applications·178 citations·filing 2005–2022
98Inventor score
Top patents by PatentIndex Score
72 records- 0194US9104581B2eDRAM refresh in a high performance cache architectureFEE MICHAEL·Filed 2010·Granted Aug 11, 2015·29 cites·11 claims
- 0293US11010210B2Controller address contention assumptionIBM·Filed 2019·Granted May 18, 2021·8 cites·20 claims
- 0391US11461151B2Controller address contention assumptionIBM·Filed 2021·Granted Oct 4, 2022·2 cites·20 claims
- 0489US8914708B2Bad wordline/array detection in memoryMEANEY PATRICK J·Filed 2012·Granted Dec 16, 2014·11 cites·11 claims
- 0589US8364899B2User-controlled targeted cache purgeIBM·Filed 2010·Granted Jan 29, 2013·13 cites·17 claims
- 0689US7502986B2Method and apparatus for collecting failure information on error correction code (ECC) protected dataIBM·Filed 2005·Granted Mar 10, 2009·15 cites·4 claims
- 0787US9507660B2Eliminate corrupted portions of cache during runtimeIBM·Filed 2016·Granted Nov 29, 2016·4 cites·1 claims
- 0885US9898407B2Configuration based cache coherency protocol selectionIBM·Filed 2015·Granted Feb 20, 2018·3 cites·11 claims
- 0985US9065481B2Bad wordline/array detection in memoryIBM·Filed 2013·Granted Jun 23, 2015·8 cites·6 claims
- 1085US8423875B2Collecting failure information on error correction code (ECC) protected dataIBM·Filed 2012·Granted Apr 16, 2013·6 cites·12 claims
- 1184US10310982B2Target cache line arbitration within a processor clusterIBM·Filed 2016·Granted Jun 4, 2019·4 cites·20 claims
- 1284US8244972B2Optimizing EDRAM refresh rates in a high performance cache architectureBRONSON TIMOTHY C·Filed 2010·Granted Aug 14, 2012·7 cites·17 claims
- 1383US9703661B2Eliminate corrupted portions of cache during runtimeIBM·Filed 2015·Granted Jul 11, 2017·3 cites·14 claims
- 1483US9244851B2Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable indexIBM·Filed 2013·Granted Jan 26, 2016·6 cites·6 claims
- 1580US11449397B2Cache array macro micro-maskingIBM·Filed 2019·Granted Sep 20, 2022·2 cites·25 claims
- 1680US9594689B2Designated cache data backup during system operationIBM·Filed 2015·Granted Mar 14, 2017·3 cites·17 claims
- 1779US8996819B2Performance optimization and dynamic resource reservation for guaranteed coherency updates in a multi-level cache hierarchyIBM·Filed 2012·Granted Mar 31, 2015·4 cites·7 claims
- 1878US8352687B2Performance optimization and dynamic resource reservation for guaranteed coherency updates in a multi-level cache hierarchyIBM·Filed 2010·Granted Jan 8, 2013·4 cites·7 claims
- 1977US10802966B2Simultaneous, non-atomic request processing within an SMP environment broadcast scope for multiply-requested data elements using real-time parallelizationIBM·Filed 2019·Granted Oct 13, 2020·2 cites·20 claims
- 2075US9348524B1Memory controlled operations under dynamic relocation of storageIBM·Filed 2014·Granted May 24, 2016·3 cites·20 claims
- 2174US8495287B2Clock-based debugging for embedded dynamic random access memory element in a processor coreCOLLURA ADAM B·Filed 2010·Granted Jul 23, 2013·4 cites·14 claims
- 2273US7934059B2Method, system and computer program product for preventing lockout and stalling conditions in a multi-node system with speculative memory fetchingIBM·Filed 2008·Granted Apr 26, 2011·6 cites·20 claims
- 2371US9678848B2Eliminate corrupted portions of cache during runtimeIBM·Filed 2016·Granted Jun 13, 2017·1 cites·1 claims
- 2471US9645904B2Dynamic cache row fail accumulation due to catastrophic failureIBM·Filed 2016·Granted May 9, 2017·1 cites·1 claims
- 2571US8327078B2Dynamic trailing edge latency absorption for fetch data forwarded from a shared data/control interfaceBERGER DEANNA POSTLES DUNN·Filed 2010·Granted Dec 4, 2012·3 cites·15 claims
- 2670US9189415B2EDRAM refresh in a high performance cache architectureIBM·Filed 2012·Granted Nov 17, 2015·2 cites·11 claims
- 2770US9047199B2Reducing penalties for cache accessing operationsIBM·Filed 2013·Granted Jun 2, 2015·2 cites·16 claims
- 2869US8560767B2Optimizing EDRAM refresh rates in a high performance cache architectureBRONSON TIMOTHY C·Filed 2012·Granted Oct 15, 2013·2 cites·8 claims
- 2969US8250308B2Cache coherency protocol with built in avoidance for conflicting responsesPAPAZOVA VESSELINA K·Filed 2008·Granted Aug 21, 2012·7 cites·19 claims
- 3068US9003125B2Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable indexAMBROLADZE EKATERINA M·Filed 2012·Granted Apr 7, 2015·2 cites·11 claims
- 3166US9600361B2Dynamic partial blocking of a cache ECC bypassIBM·Filed 2015·Granted Mar 21, 2017·1 cites·6 claims
- 3265US10824565B2Configuration based cache coherency protocol selectionIBM·Filed 2019·Granted Nov 3, 2020·0 cites·20 claims
- 3365US8645796B2Dynamic pipeline cache error correctionAMBROLADZE EKATERINA M·Filed 2010·Granted Feb 4, 2014·2 cites·20 claims
- 3464US8316284B2Collecting failure information on error correction code (ECC) protected dataO'NEILL ARTHUR J·Filed 2009·Granted Nov 20, 2012·3 cites·6 claims
- 3562US10402328B2Configuration based cache coherency protocol selectionIBM·Filed 2018·Granted Sep 3, 2019·0 cites·20 claims
- 3662US10394712B2Configuration based cache coherency protocol selectionIBM·Filed 2018·Granted Aug 27, 2019·0 cites·20 claims
- 3762US8521960B2Mitigating busy time in a high performance cacheBERGER DEANNA P·Filed 2010·Granted Aug 27, 2013·1 cites·16 claims
- 3862US7685345B2Apparatus and method for fairness arbitration for a shared pipeline in a large SMP computer systemIBM·Filed 2007·Granted Mar 23, 2010·3 cites·20 claims
- 3960US9886382B2Configuration based cache coherency protocol selectionIBM·Filed 2014·Granted Feb 6, 2018·0 cites·20 claims
- 4059US9558119B2Main memory operations in a symmetric multiprocessing computerDRAPALA GARRETT M·Filed 2010·Granted Jan 31, 2017·1 cites·15 claims
- 4158US10169260B2Multiprocessor cache buffer managementIBM·Filed 2017·Granted Jan 1, 2019·0 cites·20 claims
- 4256US9459951B2Dynamic cache row fail accumulation due to catastrophic failureIBM·Filed 2016·Granted Oct 4, 2016·0 cites·1 claims
- 4356US9298468B2Monitoring processing time in a shared pipelineIBM·Filed 2013·Granted Mar 29, 2016·0 cites·20 claims
- 4455US9792213B2Mitigating busy time in a high performance cacheIBM·Filed 2015·Granted Oct 17, 2017·0 cites·18 claims
- 4555US9600360B2Dynamic partial blocking of a cache ECC bypassIBM·Filed 2014·Granted Mar 21, 2017·0 cites·11 claims
- 4654US10833707B2Error trapping in memory structuresIBM·Filed 2019·Granted Nov 10, 2020·0 cites·18 claims
- 4754US9158694B2Mitigating busy time in a high performance cacheIBM·Filed 2012·Granted Oct 13, 2015·0 cites·8 claims
- 4853US9535787B2Dynamic cache row fail accumulation due to catastrophic failureIBM·Filed 2015·Granted Jan 3, 2017·0 cites·17 claims
- 4952US9086990B2Bitline deletionIBM·Filed 2013·Granted Jul 21, 2015·0 cites·14 claims
- 5052US9037806B2Reducing store operation busy timesIBM·Filed 2013·Granted May 19, 2015·0 cites·5 claims
Showing the top 50 of 72 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →