Inventor · disambiguated record
Dirk Scheideler
Also filed as: SCHEIDELER DIRK
16 granted patents·9 pending applications·87 citations·filing 1997–2014
91Inventor score
Top patents by PatentIndex Score
25 records- 0189US8015438B2Memory circuitQIMONDA AG·Filed 2007·Granted Sep 6, 2011·25 cites·21 claims
- 0288US8120958B2Multi-die memory, apparatus and multi-die memory stackBILGER CHRISTOPH·Filed 2007·Granted Feb 21, 2012·24 cites·13 claims
- 0380US7928525B2Integrated circuit with wireless connectionQIMONDA AG·Filed 2008·Granted Apr 19, 2011·10 cites·21 claims
- 0475US7721130B2Apparatus and method for switching an apparatus to a power saving modeQIMONDA AG·Filed 2006·Granted May 18, 2010·8 cites·33 claims
- 0556US8271827B2Memory system with extended memory density capabilityBILGER CHRISTOPH·Filed 2007·Granted Sep 18, 2012·1 cites·22 claims
- 0653US9508407B2Wiring configuration of a bus system and power wires in a memory chipMICRON TECHNOLOGY INC·Filed 2014·Granted Nov 29, 2016·1 cites·13 claims
- 0752US8724360B2Wiring configuration of a bus system and power wires in a memory chipKUZMENKA MAKSIM·Filed 2011·Granted May 13, 2014·2 cites·26 claims
- 0850US7902876B2Method and device for generating a digital data signal and use thereofQIMONDA AG·Filed 2008·Granted Mar 8, 2011·0 cites·22 claims
- 0947US8144755B2Method and apparatus for determining a skewBRUENNERT MICHAEL·Filed 2007·Granted Mar 27, 2012·0 cites·22 claims
- 1046US7936201B2Apparatus and method for providing a signal for transmission via a signal lineQIMONDA AG·Filed 2006·Granted May 3, 2011·0 cites·28 claims
- 1146US5856762APhase-locked loop with course providing damping and natural frequency independenceSIEMENS AG·Filed 1997·Granted Jan 5, 1999·12 cites·13 claims
- 1246US2011034045A1Stacking Technique for Circuit DevicesQIMONDA AG·Filed 2009·Application pending·0 cites
- 1346US2009267678A1Integrated Circuit with Improved Data RateQIMONDA AG·Filed 2008·Application pending·0 cites
- 1442US7084711B2Method and apparatus for scanning a data signal based on a direction of phase differenceINFINEON TECHNOLOGIES AG·Filed 2004·Granted Aug 1, 2006·0 cites·22 claims
- 1541US2008123792A1Apparatus and method for transmitting signals over a signal linePRETE EDOARDO·Filed 2006·Application pending·0 cites
- 1637US7920433B2Method and apparatus for storage device with a logic unit and method for manufacturing sameQIMONDA AG·Filed 2008·Granted Apr 5, 2011·0 cites·25 claims
- 1737US7215163B2Method and device for frequency division and demultiplexingINFINEON TECHNOLOGIES AG·Filed 2004·Granted May 8, 2007·2 cites·27 claims
- 1836US7405591B2Concept for interfacing a first circuit requiring a first supply voltage and a second supply circuit requiring a second supply voltageQIMONDA AG·Filed 2006·Granted Jul 29, 2008·0 cites·33 claims
- 1934US7782927B2Generating a transmission clock signal and a reception clock signal for a transceiver using an oscillatorLANTIQ DEUTSCHLAND GMBH·Filed 2004·Granted Aug 24, 2010·2 cites·2 claims
- 2034US2007183552A1Clock and data recovery circuit including first and second stagesSANDERS ANTHONY F·Filed 2006·Application pending·0 cites
- 2134US2009190432A1DRAM with Page AccessBILGER CHRISTOPH·Filed 2008·Application pending·0 cites
- 2234US2009175115A1Memory device, method for accessing a memory device and method for its manufacturingBILGER CHRISTOPH·Filed 2008·Application pending·0 cites
- 2334US2009287957A1Method for controlling a memory module and memory control unitBILGER CHRISTOPH·Filed 2008·Application pending·0 cites
- 2434US2009129189A1Method and apparatus for monitoring a memory deviceBILGER CHRISTOPH·Filed 2007·Application pending·0 cites
- 2532US2008126624A1Memory buffer and method for buffering dataPRETE EDOARDO·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →