Inventor · disambiguated record
Mark W. Hervin
Also filed as: HERVIN MARK W · HERVIN MARK WARDEN
21 granted patents·1 pending application·1,497 citations·filing 1993–2012
97Inventor score
Top patents by PatentIndex Score
22 records- 0197US6381242B1Content processorNETRAKE CORP·Filed 2000·Granted Apr 30, 2002·279 cites·13 claims
- 0296US6654373B1Content aware network apparatusNETRAKE CORP·Filed 2000·Granted Nov 25, 2003·245 cites·30 claims
- 0394US6910134B1Method and device for innoculating email infected with a virusNETRAKE CORP·Filed 2000·Granted Jun 21, 2005·138 cites·18 claims
- 0491US6957258B2Policy gatewayNETRAKE CORP·Filed 2001·Granted Oct 18, 2005·119 cites·21 claims
- 0588US7272115B2Method and apparatus for enforcing service level agreementsAUDIOCODES TEXAS INC·Filed 2002·Granted Sep 18, 2007·70 cites·13 claims
- 0688US5471598AData dependency detection and handling in a microprocessor with write bufferCYRIX CORP·Filed 1993·Granted Nov 28, 1995·139 cites·6 claims
- 0782US7002974B1Learning state machine for use in internet protocol networksNETRAKE CORP·Filed 2001·Granted Feb 21, 2006·44 cites·17 claims
- 0879US6138230AProcessor with multiple execution pipelines using pipe stage state information to control independent movement of instructions between pipe stages of an execution pipelineVIA CYRIX INC·Filed 1997·Granted Oct 24, 2000·88 cites·12 claims
- 0974US6205560B1Debug system allowing programmable selection of alternate debug mechanisms such as debug handler, SMI, or JTAGVIA CYRIX INC·Filed 1996·Granted Mar 20, 2001·76 cites·22 claims
- 1068US5805879AIn a pipelined processor, setting a segment access indicator during execution stage using exception handlingCYRIX CORP·Filed 1996·Granted Sep 8, 1998·56 cites·12 claims
- 1164US9256548B2Rule-based virtual address translation for accessing dataSTEISS DONALD EDWARD·Filed 2012·Granted Feb 9, 2016·2 cites·20 claims
- 1264US7031316B2Content processorNETRAKE CORP·Filed 2002·Granted Apr 18, 2006·8 cites·8 claims
- 1363US6073231APipelined processor with microcontrol of register translation hardwareVIA CYRIX INC·Filed 1997·Granted Jun 6, 2000·43 cites·7 claims
- 1462US5838897ADebugging a processor using data output during idle bus cyclesCYRIX CORP·Filed 1996·Granted Nov 17, 1998·40 cites·18 claims
- 1559US5835949AMethod of identifying and self-modifying codeNAT SEMICONDUCTOR CORP·Filed 1997·Granted Nov 10, 1998·36 cites·16 claims
- 1656US5524222AMicrosequencer allowing a sequence of conditional jumps without requiring the insertion of NOP or other instructionsCYRIX CORP·Filed 1994·Granted Jun 4, 1996·28 cites·7 claims
- 1754US5596735ACircuit and method for addressing segment descriptor tablesCYRIX CORP·Filed 1996·Granted Jan 21, 1997·28 cites·26 claims
- 1850US5961575AMicroprocessor having combined shift and rotate circuitNAT SEMICONDUCTOR CORP·Filed 1996·Granted Oct 5, 1999·25 cites·25 claims
- 1944US5742755AError-handling circuit and method for memory address alignment double faultCYRIX CORP·Filed 1996·Granted Apr 21, 1998·16 cites·20 claims
- 2041US2006047733A1Method for representing integer and floating point numbers in a binary orderable formatCALPONT CORP·Filed 2004·Application pending·0 cites
- 2139US5644741AProcessor with single clock decode architecture employing single microROMCYRIX CORP·Filed 1993·Granted Jul 1, 1997·10 cites·13 claims
- 2232US5794026AMicroprocessor having expedited execution of condition dependent instructionsNAT SEMICONDUCTOR CORP·Filed 1993·Granted Aug 11, 1998·7 cites·23 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →