Inventor · disambiguated record
Stephen R. Van Doren
Also filed as: VAN DOREN STEPHEN · VAN DOREN STEPHEN R · VAN DOREN STEPHEN RICHARD
90 granted patents·26 pending applications·2,279 citations·filing 1994–2025
99Inventor score
Files withINTEL CORP46HEWLETT PACKARD DEVELOPMENT CO24COMPAQ COMPUTER CORP13DIGITAL EQUIPMENT CORP8VAN DOREN STEPHEN R3
Top patents by PatentIndex Score
116 records- 0197US11245604B2Techniques to support multiple interconnect protocols for a common set of interconnect connectorsINTEL CORP·Filed 2020·Granted Feb 8, 2022·3 cites·24 claims
- 0297US11093277B2Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2020·Granted Aug 17, 2021·6 cites·25 claims
- 0396US11693691B2Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2021·Granted Jul 4, 2023·4 cites·11 claims
- 0496US9087200B2Method and apparatus to provide secure application executionMCKEEN FRANCIS X·Filed 2012·Granted Jul 21, 2015·37 cites·4 claims
- 0596US6185654B1Phantom resource memory address mapping systemCOMPAQ COMPUTER CORP·Filed 1998·Granted Feb 6, 2001·290 cites·24 claims
- 0695US11030126B2Techniques for managing access to hardware accelerator memoryINTEL CORP·Filed 2017·Granted Jun 8, 2021·13 cites·25 claims
- 0794US6249846B1Distributed data dependency stall mechanismCOMPAQ COMPUTER CORP·Filed 2000·Granted Jun 19, 2001·92 cites·8 claims
- 0894US5566325AMethod and apparatus for adaptive memory accessDIGITAL EQUIPMENT CORP·Filed 1994·Granted Oct 15, 1996·164 cites·6 claims
- 0993US10296459B1Remote atomic operations in multi-socket systemsINTEL CORP·Filed 2017·Granted May 21, 2019·9 cites·25 claims
- 1092US7174431B2Mechanism for resolving ambiguous invalidates in a computer systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Feb 6, 2007·27 cites·14 claims
- 1191US11416281B2Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2016·Granted Aug 16, 2022·4 cites·28 claims
- 1291US6055605ATechnique for reducing latency of inter-reference ordering using commit signals in a multiprocessor system having shared cachesCOMPAQ COMPUTER CORP·Filed 1997·Granted Apr 25, 2000·181 cites·17 claims
- 1390US12135981B2Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2023·Granted Nov 5, 2024·1 cites·20 claims
- 1490US10445271B2Multi-core communication acceleration using hardware queue deviceINTEL CORP·Filed 2016·Granted Oct 15, 2019·7 cites·19 claims
- 1589US11263143B2Coherent accelerator fabric controllerINTEL CORP·Filed 2017·Granted Mar 1, 2022·5 cites·25 claims
- 1689US10970238B2Non-posted write transactions for a computer busINTEL CORP·Filed 2019·Granted Apr 6, 2021·4 cites·25 claims
- 1788US6209065B1Mechanism for optimizing generation of commit-signals in a distributed shared-memory systemCOMPAQ COMPUTER CORP·Filed 1997·Granted Mar 27, 2001·144 cites·15 claims
- 1888US6108737AMethod and apparatus for reducing latency of inter-reference ordering in a multiprocessor systemCOMPAQ COMPUTER CORP·Filed 1997·Granted Aug 22, 2000·148 cites·21 claims
- 1987US6088771AMechanism for reducing latency of memory barrier operations on a multiprocessor systemDIGITAL EQUIPMENT CORP·Filed 1997·Granted Jul 11, 2000·142 cites·7 claims
- 2086US11095556B2Techniques to support multiple protocols between computer system interconnectsINTEL CORP·Filed 2017·Granted Aug 17, 2021·5 cites·25 claims
- 2185US10216668B2Technologies for a distributed hardware queue managerINTEL CORP·Filed 2016·Granted Feb 26, 2019·5 cites·29 claims
- 2285US2025315391A1Non-posted write transactions for a computer busINTEL CORP·Filed 2025·Application pending·0 cites
- 2384US10437616B2Method, apparatus, system for optimized work submission to an accelerator work queueINTEL CORP·Filed 2016·Granted Oct 8, 2019·4 cites·16 claims
- 2483US9418009B2Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memoryINTEL CORP·Filed 2013·Granted Aug 16, 2016·7 cites·21 claims
- 2583US6990559B2Mechanism for resolving ambiguous invalidates in a computer systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Jan 24, 2006·30 cites·14 claims
- 2683US6801986B2Livelock prevention by delaying surrender of ownership upon intervening ownership request during load locked / store conditional atomic memory operationHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Oct 5, 2004·37 cites·24 claims
- 2783US6085263AMethod and apparatus for employing commit-signals and prefetching to maintain inter-reference ordering in a high-performance I/O processorCOMPAQ COMPUTER CORP·Filed 1997·Granted Jul 4, 2000·111 cites·18 claims
- 2882US11204867B2PCIe controller with extensions to provide coherent memory mapping between accelerator memory and host memoryINTEL CORP·Filed 2017·Granted Dec 21, 2021·3 cites·25 claims
- 2982US7177987B2System and method for responses between different cache coherency protocolsHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Feb 13, 2007·31 cites·33 claims
- 3082US2025123881A1Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2024·Application pending·0 cites
- 3181US10102380B2Method and apparatus to provide secure application executionINTEL CORP·Filed 2013·Granted Oct 16, 2018·4 cites·10 claims
- 3279US10572260B2Spatial and temporal merging of remote atomic operationsINTEL CORP·Filed 2017·Granted Feb 25, 2020·2 cites·22 claims
- 3379US6125429ACache memory exchange optimized memory organization for a computer systemCOMPAQ COMPUTER CORP·Filed 1998·Granted Sep 26, 2000·75 cites·7 claims
- 3479US6085294ADistributed data dependency stall mechanismCOMPAQ COMPUTER CORP·Filed 1997·Granted Jul 4, 2000·75 cites·27 claims
- 3576US12332813B2Non-posted write transactions for a computer busINTEL CORP·Filed 2022·Granted Jun 17, 2025·0 cites·29 claims
- 3676US11138112B2Remote atomic operations in multi-socket systemsINTEL CORP·Filed 2019·Granted Oct 5, 2021·1 cites·20 claims
- 3774US10929323B2Multi-core communication acceleration using hardware queue deviceINTEL CORP·Filed 2019·Granted Feb 23, 2021·1 cites·25 claims
- 3874US7395374B2System and method for conflict responses in a cache coherency protocol with ordering point migrationHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Jul 1, 2008·18 cites·35 claims
- 3974US7149852B2System and method for blocking data responsesHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Dec 12, 2006·18 cites·34 claims
- 4074US6353876B1Cache memory exchange optimized memory organization for a computer systemCOMPAQ INFORMATION TECHNOLOGIE·Filed 2000·Granted Mar 5, 2002·17 cites·8 claims
- 4173US6892290B2Linked-list early race resolution mechanismHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted May 10, 2005·17 cites·19 claims
- 4273US6286090B1Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetchesCOMPAQ COMPUTER CORP·Filed 1998·Granted Sep 4, 2001·66 cites·10 claims
- 4373US5761731AMethod and apparatus for performing atomic transactions in a shared memory multi processor systemDIGITAL EQUIPMENT CORP·Filed 1997·Granted Jun 2, 1998·64 cites·14 claims
- 4472US10884195B2Techniques to support multiple interconnect protocols for a common set of interconnect connectorsINTEL CORP·Filed 2016·Granted Jan 5, 2021·0 cites·25 claims
- 4572US7143245B2System and method for read migratory optimization in a cache coherency protocolHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Nov 28, 2006·16 cites·31 claims
- 4672US5537575ASystem for handling cache memory victim data which transfers data from cache to the interface while CPU performs a cache lookup using cache status informationFiled 1994·Granted Jul 16, 1996·61 cites·4 claims
- 4771US11726927B2Method, apparatus, system for early page granular hints from a PCIe deviceINTEL CORP·Filed 2022·Granted Aug 15, 2023·0 cites·20 claims
- 4871US11537520B2Remote atomic operations in multi-socket systemsINTEL CORP·Filed 2021·Granted Dec 27, 2022·0 cites·24 claims
- 4971US11513979B2Non-posted write transactions for a computer busINTEL CORP·Filed 2021·Granted Nov 29, 2022·0 cites·30 claims
- 5069US6895476B2Retry-based late race resolution mechanism for a computer systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted May 17, 2005·14 cites·19 claims
Showing the top 50 of 116 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Stephen R. Van Doren files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →