Inventor · disambiguated record
Robert K. Montoye
Also filed as: MONTOYE ROBERT · MONTOYE ROBERT K · MONTOYE ROBERT KEVIN
120 granted patents·16 pending applications·2,826 citations·filing 1985–2023
99Inventor score
Top patents by PatentIndex Score
136 records- 0199US8107276B2Resistive memory devices having a not-and (NAND) structureBREITWISCH MATTHEW J·Filed 2009·Granted Jan 31, 2012·246 cites·16 claims
- 0299US8059438B2Content addressable memory array programmed to perform logic operationsCHANG LELAND·Filed 2009·Granted Nov 15, 2011·416 cites·17 claims
- 0399US6507115B2Multi-chip integrated circuit moduleIBM·Filed 2000·Granted Jan 14, 2003·312 cites·22 claims
- 0498US8020073B2Dynamic memory architecture employing passive expiration of dataIBM·Filed 2007·Granted Sep 13, 2011·99 cites·20 claims
- 0596US8493093B1Time division multiplexed limited switch dynamic logicCHANG LELAND·Filed 2012·Granted Jul 23, 2013·14 cites·20 claims
- 0696US7290203B2Dynamic memory architecture employing passive expiration of dataIBM·Filed 2004·Granted Oct 30, 2007·101 cites·13 claims
- 0795US7793081B2Implementing instruction set architectures with non-contiguous register file specifiersIBM·Filed 2008·Granted Sep 7, 2010·34 cites·5 claims
- 0895US7421566B2Implementing instruction set architectures with non-contiguous register file specifiersIBM·Filed 2006·Granted Sep 2, 2008·38 cites·1 claims
- 0994US11687148B1Stacked, reconfigurable co-regulation of processing units for ultra-wide DVFSIBM·Filed 2022·Granted Jun 27, 2023·5 cites·20 claims
- 1094US8166281B2Implementing instruction set architectures with non-contiguous register file specifiersGSCHWIND MICHAEL KARL·Filed 2009·Granted Apr 24, 2012·30 cites·16 claims
- 1194US4969118AFloating point unit for calculating A=XY+Z having simultaneous multiply and addIBM·Filed 1989·Granted Nov 6, 1990·165 cites·3 claims
- 1293US9818058B2Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptationIBM·Filed 2016·Granted Nov 14, 2017·13 cites·15 claims
- 1393US8918623B2Implementing instruction set architectures with non-contiguous register file specifiersGSCHWIND MICHAEL KARL·Filed 2012·Granted Dec 23, 2014·23 cites·18 claims
- 1493US8856055B2Reconfigurable and customizable general-purpose circuits for neural networksBREZZO BERNARD V·Filed 2011·Granted Oct 7, 2014·38 cites·27 claims
- 1593US7106620B2Memory cell having improved read stabilityIBM·Filed 2005·Granted Sep 12, 2006·32 cites·21 claims
- 1692US7298193B2Methods and arrangements to adjust a duty cycleIBM·Filed 2006·Granted Nov 20, 2007·22 cites·20 claims
- 1792US6650145B2Circuits and systems for limited switch dynamic logicIBM·Filed 2002·Granted Nov 18, 2003·47 cites·24 claims
- 1891US6326696B1Electronic package with interconnected chipsIBM·Filed 1998·Granted Dec 4, 2001·107 cites·22 claims
- 1989US6690204B1Limited switch dynamic logic circuitIBM·Filed 2002·Granted Feb 10, 2004·37 cites·24 claims
- 2089US5319590AApparatus for storing "Don't Care" in a content addressable memory cellHAL COMPUTER SYSTEMS INC·Filed 1992·Granted Jun 7, 1994·76 cites·12 claims
- 2188US9373073B2Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptationIBM·Filed 2012·Granted Jun 21, 2016·20 cites·31 claims
- 2288US7472226B1Methods involving memory cachesIBM·Filed 2008·Granted Dec 30, 2008·18 cites·3 claims
- 2388US6262885B1Portable computing device having a display movable thereaboutIBM·Filed 1998·Granted Jul 17, 2001·149 cites·24 claims
- 2488US5266849ATri state buffer circuit for dual power systemHAL COMPUTER SYSTEMS INC·Filed 1992·Granted Nov 30, 1993·53 cites·11 claims
- 2587US8893095B2Methods for generating code for an architecture encoding an extended register specificationGSCHWIND MICHAEL KARL·Filed 2012·Granted Nov 18, 2014·7 cites·12 claims
- 2687US8629705B2Low voltage signalingCHANG LELAND·Filed 2010·Granted Jan 14, 2014·9 cites·21 claims
- 2786US8687398B2Sense scheme for phase change material content addressable memoryCHANG LELAND·Filed 2012·Granted Apr 1, 2014·10 cites·19 claims
- 2886US8605489B2Enhanced data retention mode for dynamic memoriesREOHR WILLIAM ROBERT·Filed 2011·Granted Dec 10, 2013·10 cites·25 claims
- 2985US8604832B1Time division multiplexed limited switch dynamic logicCHANG LELAND·Filed 2012·Granted Dec 10, 2013·4 cites·20 claims
- 3085US7242629B2High speed latch circuits using gated diodesIBM·Filed 2006·Granted Jul 10, 2007·14 cites·15 claims
- 3183US9740659B2Merging and sorting arrays on an SIMD processorIBM·Filed 2014·Granted Aug 22, 2017·7 cites·20 claims
- 3283US9239984B2Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural networkIBM·Filed 2012·Granted Jan 19, 2016·11 cites·20 claims
- 3383US8261138B2Test structure for characterizing multi-port static random access memory and register file arraysCHANG LELAND·Filed 2006·Granted Sep 4, 2012·12 cites·12 claims
- 3483US8248152B2Switched capacitor voltage convertersDENNARD ROBERT H·Filed 2009·Granted Aug 21, 2012·12 cites·9 claims
- 3583US7129754B2Controlled load limited switch dynamic logic circuitryIBM·Filed 2005·Granted Oct 31, 2006·13 cites·19 claims
- 3682US10628732B2Reconfigurable and customizable general-purpose circuits for neural networksIBM·Filed 2016·Granted Apr 21, 2020·3 cites·18 claims
- 3782US8892487B2Electronic synapses for reinforcement learningCHANG LELAND·Filed 2010·Granted Nov 18, 2014·14 cites·25 claims
- 3882US8295056B2Silicon carrier structure and method of forming sameANDRY PAUL STEPHEN·Filed 2009·Granted Oct 23, 2012·9 cites·15 claims
- 3981US7526610B1Sectored cache memoryIBM·Filed 2008·Granted Apr 28, 2009·10 cites·2 claims
- 4081US7116594B2Sense amplifier circuits and high speed latch circuits using gated diodesIBM·Filed 2004·Granted Oct 3, 2006·23 cites·18 claims
- 4180US7349288B1Ultra high-speed Nor-type LSDL/Domino combined address decoderIBM·Filed 2006·Granted Mar 25, 2008·12 cites·20 claims
- 4279US10331998B2Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural networkIBM·Filed 2015·Granted Jun 25, 2019·3 cites·15 claims
- 4379US7631167B2System for SIMD-oriented management of register maps for map-based indirect register-file accessIBM·Filed 2008·Granted Dec 8, 2009·8 cites·10 claims
- 4479US7282960B2Dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clockIBM·Filed 2005·Granted Oct 16, 2007·11 cites·19 claims
- 4578US9496854B2High-speed latch circuits by selective use of large gate pitchIBM·Filed 2015·Granted Nov 15, 2016·2 cites·4 claims
- 4678US8638598B1Multi-bit resistance measurementLAM CHUNG H·Filed 2012·Granted Jan 28, 2014·6 cites·8 claims
- 4778US8446748B2Content addressable memories with wireline compensationLAM CHUNG HON·Filed 2011·Granted May 21, 2013·7 cites·16 claims
- 4877US6199126B1Processor transparent on-the-fly instruction stream decompressionIBM·Filed 1997·Granted Mar 6, 2001·85 cites·5 claims
- 4976US6306686B1Method of fabricating an electronic package with interconnected chipsIBM·Filed 2000·Granted Oct 23, 2001·22 cites·5 claims
- 5075US10042876B2Sort-merge-join on a large architected register fileIBM·Filed 2014·Granted Aug 7, 2018·4 cites·13 claims
Showing the top 50 of 136 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →