Inventor · disambiguated record
Derek J. Lentz
Also filed as: LENTZ DEREK · LENTZ DEREK J
77 granted patents·3 pending applications·3,556 citations·filing 1991–2020
99Inventor score
Files withSEIKO EPSON CORP64SAMSUNG ELECTRONICS CO LTD11GARG SANJIV2INTELLECTUAL VENTURE FUNDING LLC1NGUYEN LE TRONG1
Top patents by PatentIndex Score
80 records- 0196US6611908B2Microprocessor architecture capable of supporting multiple heterogeneous processorsSEIKO EPSON CORP·Filed 2001·Granted Aug 26, 2003·83 cites·12 claims
- 0296US5440752AMicroprocessor architecture with a switch network for data transfer between cache, memory port, and IOUSEIKO EPSON CORP·Filed 1991·Granted Aug 8, 1995·170 cites·35 claims
- 0395US7739482B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2006·Granted Jun 15, 2010·26 cites·18 claims
- 0495US5560032AHigh-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distributionSEIKO EPSON CORP·Filed 1995·Granted Sep 24, 1996·193 cites·29 claims
- 0595US5539911AHigh-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1992·Granted Jul 23, 1996·133 cites·56 claims
- 0692US6647485B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2001·Granted Nov 11, 2003·42 cites·40 claims
- 0792US6272579B1Microprocessor architecture capable of supporting multiple heterogeneous processorsSEIKO EPSON CORP·Filed 1999·Granted Aug 7, 2001·120 cites·8 claims
- 0891US5689720AHigh-performance superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1996·Granted Nov 18, 1997·90 cites·11 claims
- 0991US5649230ASystem for transferring data using value in hardware FIFO'S unused data start pointer to update virtual FIFO'S start address pointer for fast context switchingSEIKO EPSON CORP·Filed 1995·Granted Jul 15, 1997·161 cites·33 claims
- 1091US5533185APixel modification unit for use as a functional unit in a superscalar microprocessorSEIKO EPSON CORP·Filed 1993·Granted Jul 2, 1996·116 cites·5 claims
- 1191US5493687ARISC microprocessor architecture implementing multiple typed register setsSEIKO EPSON CORP·Filed 1991·Granted Feb 20, 1996·103 cites·5 claims
- 1290US6965987B2System and method for handling load and/or store operations in a superscalar microprocessorSEIKO EPSON CORP·Filed 2003·Granted Nov 15, 2005·43 cites·58 claims
- 1390US5560035ARISC microprocessor architecture implementing multiple typed register setsSEIKO EPSON CORP·Filed 1995·Granted Sep 24, 1996·105 cites·8 claims
- 1489US6986024B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2002·Granted Jan 10, 2006·28 cites·24 claims
- 1588US6954844B2Microprocessor architecture capable of supporting multiple heterogeneous processorsSEIKO EPSON CORP·Filed 2003·Granted Oct 11, 2005·29 cites·23 claims
- 1688US6915412B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2002·Granted Jul 5, 2005·25 cites·26 claims
- 1788US5754800AMulti processor system having dynamic priority based on row match of previously serviced address, number of times denied service and number of times serviced without interruptionSEIKO EPSON CORP·Filed 1995·Granted May 19, 1998·86 cites·6 claims
- 1887US7685402B2RISC microprocessor architecture implementing multiple typed register setsGARG SANJIV·Filed 2007·Granted Mar 23, 2010·10 cites·12 claims
- 1987US7657712B2Microprocessor architecture capable of supporting multiple heterogeneous processorsSEIKO EPSON CORP·Filed 2005·Granted Feb 2, 2010·10 cites·12 claims
- 2087US6948052B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2002·Granted Sep 20, 2005·23 cites·39 claims
- 2187US5961629AHigh performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1998·Granted Oct 5, 1999·135 cites·27 claims
- 2287US5446836APolygon rasterizationSEIKO EPSON CORP·Filed 1992·Granted Aug 29, 1995·106 cites·20 claims
- 2386US7721070B2High-performance, superscalar-based computer system with out-of-order instruction executionNGUYEN LE TRONG·Filed 2008·Granted May 18, 2010·10 cites·21 claims
- 2486US7162610B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2003·Granted Jan 9, 2007·21 cites·35 claims
- 2586US5515494AGraphics control planes for windowing and other display operationsSEIKO EPSON CORP·Filed 1994·Granted May 7, 1996·72 cites·19 claims
- 2685US6959375B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2002·Granted Oct 25, 2005·19 cites·10 claims
- 2785US5649173AHardware architecture for image generation and manipulationSEIKO EPSON CORP·Filed 1995·Granted Jul 15, 1997·83 cites·19 claims
- 2884US6934829B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2003·Granted Aug 23, 2005·17 cites·21 claims
- 2984US6249856B1RISC microprocessor architecture implementing multiple typed register setsSEIKO EPSON CORP·Filed 2000·Granted Jun 19, 2001·26 cites·17 claims
- 3082US5448705ARISC microprocessor architecture implementing fast trap and exception stateSEIKO EPSON CORP·Filed 1993·Granted Sep 5, 1995·79 cites·3 claims
- 3182US5428779ASystem and method for supporting context switching within a multiprocessor system having functional blocks that generate state programs with coded register load instructionsSEIKO EPSON CORP·Filed 1992·Granted Jun 27, 1995·95 cites·4 claims
- 3281US6219763B1System and method for adjusting priorities associated with multiple devices seeking access to a memory array unitSEIKO EPSON CORP·Filed 1999·Granted Apr 17, 2001·55 cites·4 claims
- 3381US5790134AHardware architecture for image generation and manipulationSEIKO EPSON CORP·Filed 1997·Granted Aug 4, 1998·66 cites·15 claims
- 3481US5444853ASystem and method for transferring data between a plurality of virtual FIFO's and a peripheral via a hardware FIFO and selectively updating control information associated with the virtual FIFO'sSEIKO EPSON CORP·Filed 1992·Granted Aug 22, 1995·78 cites·21 claims
- 3580US7555632B2High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distributionSEIKO EPSON CORP·Filed 2005·Granted Jun 30, 2009·6 cites·23 claims
- 3680US6941447B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2003·Granted Sep 6, 2005·13 cites·23 claims
- 3780US6128723AHigh-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1999·Granted Oct 3, 2000·42 cites·27 claims
- 3879US7941635B2High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distributionSEIKO EPSON CORP·Filed 2006·Granted May 10, 2011·5 cites·5 claims
- 3979US7028161B2High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distributionSEIKO EPSON CORP·Filed 2001·Granted Apr 11, 2006·17 cites·39 claims
- 4079US6038654AHigh performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1999·Granted Mar 14, 2000·39 cites·80 claims
- 4179US5604865AMicroprocessor architecture with a switch network for data transfer between cache, memory port, and IOUSEIKO EPSON CORP·Filed 1995·Granted Feb 18, 1997·50 cites·20 claims
- 4279US5481685ARISC microprocessor architecture implementing fast trap and exception stateSEIKO EPSON CORP·Filed 1994·Granted Jan 2, 1996·66 cites·16 claims
- 4378US10635439B2Efficient interface and transport mechanism for binding bindless shader programs to run-time specified graphics pipeline configurations and objectsSAMSUNG ELECTRONICS CO LTD·Filed 2018·Granted Apr 28, 2020·2 cites·26 claims
- 4478US9972124B2Elimination of minimal use threads via quad mergingSAMSUNG ELECTRONICS CO LTD·Filed 2017·Granted May 15, 2018·3 cites·18 claims
- 4578US8019975B2System and method for handling load and/or store operations in a superscalar microprocessorSEIKO EPSON CORP·Filed 2005·Granted Sep 13, 2011·5 cites·59 claims
- 4677US6092181AHigh-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1997·Granted Jul 18, 2000·37 cites·62 claims
- 4777US5499384AInput output control unit having dedicated paths for controlling the input and output of data between host processor and external deviceSEIKO EPSON CORP·Filed 1992·Granted Mar 12, 1996·82 cites·42 claims
- 4876US6272619B1High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1999·Granted Aug 7, 2001·34 cites·80 claims
- 4976US6256720B1High performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1999·Granted Jul 3, 2001·34 cites·80 claims
- 5076US5838986ARISC microprocessor architecture implementing multiple typed register setsSEIKO EPSON CORP·Filed 1997·Granted Nov 17, 1998·42 cites·30 claims
Showing the top 50 of 80 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Derek J. Lentz files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →