Inventor · disambiguated record
Joe W. Zhao
Also filed as: ZHAO JOE W
26 granted patents·999 citations·filing 1995–2011
97Inventor score
Top patents by PatentIndex Score
26 records- 0195US6028015AProcess for treating damaged surfaces of low dielectric constant organo silicon oxide insulation material to inhibit moisture absorptionLSI LOGIC CORP·Filed 1999·Granted Feb 22, 2000·173 cites·14 claims
- 0294US6204192B1Plasma cleaning process for openings formed in at least one low dielectric constant insulation layer over copper metallization in integrated circuit structuresLSI LOGIC CORP·Filed 1999·Granted Mar 20, 2001·166 cites·17 claims
- 0390US6368979B1Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structureLSI LOGIC CORP·Filed 2000·Granted Apr 9, 2002·52 cites·26 claims
- 0489US5660682APlasma clean with hydrogen gasLSI LOGIC CORP·Filed 1996·Granted Aug 26, 1997·100 cites·18 claims
- 0588US6232658B1Process to prevent stress cracking of dielectric films on semiconductor wafersLSI LOGIC CORP·Filed 1999·Granted May 15, 2001·93 cites·20 claims
- 0684US5926720AConsistent alignment mark profiles on semiconductor wafers using PVD shadowingLSI LOGIC CORP·Filed 1997·Granted Jul 20, 1999·64 cites·16 claims
- 0779US5770520AMethod of making a barrier layer for via or contact opening of integrated circuit structureLSI LOGIC CORP·Filed 1996·Granted Jun 23, 1998·57 cites·21 claims
- 0878US8000519B1Method of metal pattern inspection verificationXILINX INC·Filed 2007·Granted Aug 16, 2011·7 cites·19 claims
- 0975US8402412B1Increasing circuit speed and reducing circuit leakage by utilizing a local surface temperature effectCHEN CINTI X·Filed 2011·Granted Mar 19, 2013·4 cites·16 claims
- 1071US5994775AMetal-filled via/contact opening with thin barrier layers in integrated circuit structure for fast response, and process for making sameLSI LOGIC CORP·Filed 1997·Granted Nov 30, 1999·39 cites·15 claims
- 1170US7020860B1Method for monitoring and improving integrated circuit fabrication using FPGAsXILINX INC·Filed 2004·Granted Mar 28, 2006·15 cites·21 claims
- 1270US6756674B1Low dielectric constant silicon oxide-based dielectric layer for integrated circuit structures having improved compatibility with via filler materials, and method of making sameLSI LOGIC CORP·Filed 1999·Granted Jun 29, 2004·36 cites·24 claims
- 1365US8311659B1Identifying non-randomness in integrated circuit product yieldCHEN CINTI X·Filed 2009·Granted Nov 13, 2012·2 cites·11 claims
- 1463US5956613AMethod for improvement of TiN CVD film qualityLSI LOGIC CORP·Filed 1995·Granted Sep 21, 1999·27 cites·13 claims
- 1562US6157087AConsistent alignment mark profiles on semiconductor wafers using metal organic chemical vapor deposition titanium nitride protective layerLSI LOGIC CORP·Filed 1999·Granted Dec 5, 2000·22 cites·5 claims
- 1661US8166445B1Estimating Icc current temperature scaling factor of an integrated circuitCHEN CINTI X·Filed 2009·Granted Apr 24, 2012·2 cites·20 claims
- 1761US6297555B1Method to obtain a low resistivity and conformity chemical vapor deposition titanium filmLSI LOGIC CORP·Filed 1998·Granted Oct 2, 2001·22 cites·34 claims
- 1859US5895267AMethod to obtain a low resistivity and conformity chemical vapor deposition titanium filmLSI LOGIC CORP·Filed 1997·Granted Apr 20, 1999·20 cites·19 claims
- 1957US6239499B1Consistent alignment mark profiles on semiconductor wafers using PVD shadowingLSI LOGIC CORP·Filed 1998·Granted May 29, 2001·18 cites·15 claims
- 2055US5789028AMethod for eliminating peeling at end of semiconductor substrate in metal organic chemical vapor deposition of titanium nitrideLSI LOGIC CORP·Filed 1997·Granted Aug 4, 1998·17 cites·9 claims
- 2152US5635244AMethod of forming a layer of material on a waferLSI LOGIC CORP·Filed 1995·Granted Jun 3, 1997·16 cites·11 claims
- 2250US6059637AProcess for abrasive removal of copper from the back surface of a silicon substrateLSI LOGIC CORP·Filed 1997·Granted May 9, 2000·15 cites·20 claims
- 2349US6060787AConsistent alignment mark profiles on semiconductor wafers using fine grain tungsten protective layerLSI LOGIC CORP·Filed 1999·Granted May 9, 2000·12 cites·14 claims
- 2447US5981352AConsistent alignment mark profiles on semiconductor wafers using fine grain tungsten protective layerLSI LOGIC CORP·Filed 1997·Granted Nov 9, 1999·11 cites·11 claims
- 2542US5966613AConsistent alignment mark profiles on semiconductor wafers using metal organic chemical vapor deposition titanium nitride protectiveLSI CORP·Filed 1997·Granted Oct 12, 1999·8 cites·12 claims
- 2631US5953631ALow stress, highly conformal CVD metal thin filmLSI LOGIC CORP·Filed 1996·Granted Sep 14, 1999·1 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →