Inventor · disambiguated record
Michael Putrino
Also filed as: PUTRINO MICHAEL
19 granted patents·380 citations·filing 1987–1999
95Inventor score
Technology areasG06F
Files withIBM18
Top patents by PatentIndex Score
19 records- 0176US5805475ALoad-store unit and method of loading and storing single-precision floating-point registers in a double-precision architectureIBM·Filed 1997·Granted Sep 8, 1998·75 cites·21 claims
- 0263US5611063AMethod for executing speculative load instructions in high-performance processorsIBM·Filed 1996·Granted Mar 11, 1997·44 cites·11 claims
- 0363US5375078AArithmetic unit for performing XY+B operationIBM·Filed 1992·Granted Dec 20, 1994·39 cites·21 claims
- 0459US6324638B1Processor having vector processing capability and method for executing a vector instruction in a processorIBM·Filed 1999·Granted Nov 27, 2001·35 cites·22 claims
- 0559US4924422AMethod and apparatus for modified carry-save determination of arithmetic/logic zero resultsIBM·Filed 1988·Granted May 8, 1990·27 cites·9 claims
- 0650US5872948AProcessor and method for out-of-order execution of instructions based upon an instruction parameterIBM·Filed 1996·Granted Feb 16, 1999·23 cites·24 claims
- 0749US4914617AHigh performance parallel binary byte adderIBM·Filed 1987·Granted Apr 3, 1990·17 cites·20 claims
- 0848US5765191AMethod for implementing a four-way least recently used (LRU) mechanism in high-performanceIBM·Filed 1996·Granted Jun 9, 1998·20 cites·8 claims
- 0944US4947359AApparatus and method for prediction of zero arithmetic/logic resultsIBM·Filed 1989·Granted Aug 7, 1990·14 cites·12 claims
- 1043US5678016AProcessor and method for managing execution of an instruction which determine subsequent to dispatch if an instruction is subject to serializationIBM·Filed 1995·Granted Oct 14, 1997·16 cites·17 claims
- 1139US5754811AInstruction dispatch queue for improved instruction cache to queue timingFiled 1996·Granted May 19, 1998·11 cites·18 claims
- 1239US5732005ASingle-precision, floating-point register array for floating-point units performing double-precision operations by emulationIBM·Filed 1995·Granted Mar 24, 1998·12 cites·13 claims
- 1338US6098168ASystem for completing instruction out-of-order which performs target address comparisons prior to dispatchIBM·Filed 1998·Granted Aug 1, 2000·10 cites·14 claims
- 1438US5805916AMethod and apparatus for dynamic allocation of registers for intermediate floating-point resultsIBM·Filed 1996·Granted Sep 8, 1998·10 cites·13 claims
- 1536US5809323AMethod and apparatus for executing fixed-point instructions within idle execution units of a superscalar processorIBM·Filed 1995·Granted Sep 15, 1998·9 cites·13 claims
- 1633US6519620B1Saturation select apparatus and method thereforIBM·Filed 1999·Granted Feb 11, 2003·7 cites·22 claims
- 1732US5805487AMethod and system for fast determination of sticky and guard bitsIBM·Filed 1996·Granted Sep 8, 1998·4 cites·39 claims
- 1832US4914579AApparatus for branch prediction for computer instructionsIBM·Filed 1988·Granted Apr 3, 1990·5 cites·6 claims
- 1930US4924424AParity prediction for binary adders with selectionIBM·Filed 1988·Granted May 8, 1990·2 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →