Inventor · disambiguated record
Robert J. Mears
Also filed as: MEARS ROBERT · MEARS ROBERT J
90 granted patents·36 pending applications·5,795 citations·filing 2001–2025
99Inventor score
Top patents by PatentIndex Score
126 records- 0199US11978771B2Gate-all-around (GAA) device including a superlatticeATOMERA INC·Filed 2022·Granted May 7, 2024·7 cites·21 claims
- 0299US11848356B2Method for making semiconductor device including superlattice with oxygen and carbon monolayersATOMERA INC·Filed 2021·Granted Dec 19, 2023·6 cites·21 claims
- 0399US11837634B2Semiconductor device including superlattice with oxygen and carbon monolayersATOMERA INC·Filed 2021·Granted Dec 5, 2023·10 cites·21 claims
- 0499US11742202B2Methods for making radio frequency (RF) semiconductor devices including a ground plane layer having a superlatticeATOMERA INC·Filed 2022·Granted Aug 29, 2023·10 cites·23 claims
- 0599US11430869B2Method for making superlattice structures with reduced defect densitiesATOMERA INC·Filed 2020·Granted Aug 30, 2022·8 cites·13 claims
- 0699US10593761B1Method for making a semiconductor device having reduced contact resistanceATOMERA INC·Filed 2018·Granted Mar 17, 2020·51 cites·21 claims
- 0799US10580866B1Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistanceATOMERA INC·Filed 2018·Granted Mar 3, 2020·49 cites·21 claims
- 0899US10453945B2Semiconductor device including resonant tunneling diode structure having a superlatticeATOMERA INC·Filed 2017·Granted Oct 22, 2019·45 cites·23 claims
- 0999US10361243B2Method for making CMOS image sensor including superlattice to enhance infrared light absorptionATOMERA INC·Filed 2017·Granted Jul 23, 2019·44 cites·20 claims
- 1099US10276625B1CMOS image sensor including superlattice to enhance infrared light absorptionATOMERA INC·Filed 2017·Granted Apr 30, 2019·54 cites·20 claims
- 1199US10249745B2Method for making a semiconductor device including a resonant tunneling diode structure having a superlatticeATOMERA INC·Filed 2017·Granted Apr 2, 2019·52 cites·22 claims
- 1299US10170560B2Semiconductor devices with enhanced deterministic doping and related methodsATOMERA INC·Filed 2017·Granted Jan 1, 2019·60 cites·21 claims
- 1399US10170604B2Method for making a semiconductor device including a resonant tunneling diode with electron mean free path control layersATOMERA INC·Filed 2017·Granted Jan 1, 2019·60 cites·20 claims
- 1499US10170603B2Semiconductor device including a resonant tunneling diode structure with electron mean free path control layersATOMERA INC·Filed 2017·Granted Jan 1, 2019·61 cites·20 claims
- 1599US10109479B1Method of making a semiconductor device with a buried insulating layer formed by annealing a superlatticeATOMERA INC·Filed 2017·Granted Oct 23, 2018·82 cites·23 claims
- 1699US9941359B2Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methodsATOMERA INC·Filed 2016·Granted Apr 10, 2018·73 cites·23 claims
- 1799US9899479B2Semiconductor devices with superlattice layers providing halo implant peak confinement and related methodsATOMERA INC·Filed 2016·Granted Feb 20, 2018·89 cites·21 claims
- 1899US7435988B2Semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channelMEARS TECHNOLOGIES INC·Filed 2005·Granted Oct 14, 2008·110 cites·37 claims
- 1999US7303948B2Semiconductor device including MOSFET having band-engineered superlatticeMEARS TECHNOLOGIES INC·Filed 2005·Granted Dec 4, 2007·110 cites·11 claims
- 2099US7265002B2Method for making a semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channelRJ MEARS LLC·Filed 2005·Granted Sep 4, 2007·114 cites·39 claims
- 2198US11664427B2Vertical semiconductor device with enhanced contact structure and associated methodsATOMERA INC·Filed 2022·Granted May 30, 2023·7 cites·32 claims
- 2298US11387325B2Vertical semiconductor device with enhanced contact structure and associated methodsATOMERA INC·Filed 2020·Granted Jul 12, 2022·12 cites·35 claims
- 2398US10879356B2Method for making a semiconductor device including enhanced contact structures having a superlatticeATOMERA INC·Filed 2019·Granted Dec 29, 2020·21 cites·26 claims
- 2498US10868120B1Method for making a varactor with hyper-abrupt junction region including a superlatticeATOMERA INC·Filed 2019·Granted Dec 15, 2020·31 cites·25 claims
- 2598US10854717B2Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistanceATOMERA INC·Filed 2018·Granted Dec 1, 2020·32 cites·20 claims
- 2698US10847618B2Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistanceATOMERA INC·Filed 2018·Granted Nov 24, 2020·33 cites·20 claims
- 2798US10840337B2Method for making a FINFET having reduced contact resistanceATOMERA INC·Filed 2018·Granted Nov 17, 2020·31 cites·21 claims
- 2898US10840336B2Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methodsATOMERA INC·Filed 2018·Granted Nov 17, 2020·31 cites·17 claims
- 2998US10840335B2Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistanceATOMERA INC·Filed 2018·Granted Nov 17, 2020·31 cites·23 claims
- 3098US10840388B1Varactor with hyper-abrupt junction region including a superlatticeATOMERA INC·Filed 2019·Granted Nov 17, 2020·33 cites·23 claims
- 3198US10825901B1Semiconductor devices including hyper-abrupt junction region including a superlatticeATOMERA INC·Filed 2019·Granted Nov 3, 2020·32 cites·17 claims
- 3298US10825902B1Varactor with hyper-abrupt junction region including spaced-apart superlatticesATOMERA INC·Filed 2019·Granted Nov 3, 2020·30 cites·22 claims
- 3398US10818755B2Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistanceATOMERA INC·Filed 2018·Granted Oct 27, 2020·33 cites·21 claims
- 3498US10811498B2Method for making superlattice structures with reduced defect densitiesATOMERA INC·Filed 2018·Granted Oct 20, 2020·35 cites·16 claims
- 3598US10777451B2Semiconductor device including enhanced contact structures having a superlatticeATOMERA INC·Filed 2019·Granted Sep 15, 2020·30 cites·27 claims
- 3698US10741436B2Method for making a semiconductor device including non-monocrystalline stringer adjacent a superlattice-sti interfaceATOMERA INC·Filed 2018·Granted Aug 11, 2020·30 cites·23 claims
- 3798US10727049B2Method for making a semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlatticeATOMERA INC·Filed 2018·Granted Jul 28, 2020·30 cites·25 claims
- 3898US10580867B1FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistanceATOMERA INC·Filed 2018·Granted Mar 3, 2020·49 cites·22 claims
- 3998US10566191B1Semiconductor device including superlattice structures with reduced defect densitiesATOMERA INC·Filed 2018·Granted Feb 18, 2020·51 cites·22 claims
- 4098US10468245B2Semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlatticeATOMERA INC·Filed 2018·Granted Nov 5, 2019·46 cites·25 claims
- 4198US10084045B2Semiconductor device including a superlattice and replacement metal gate structure and related methodsATOMERA INC·Filed 2017·Granted Sep 25, 2018·72 cites·22 claims
- 4298US9972685B2Vertical semiconductor devices including superlattice punch through stop layer and related methodsATOMERA INC·Filed 2015·Granted May 15, 2018·64 cites·12 claims
- 4398US9406753B2Semiconductor devices including superlattice depletion layer stack and related methodsATOMERA INC·Filed 2014·Granted Aug 2, 2016·104 cites·22 claims
- 4498US8389974B2Multiple-wavelength opto-electronic device including a superlatticeMEARS ROBERT J·Filed 2011·Granted Mar 5, 2013·109 cites·34 claims
- 4598US7880161B2Multiple-wavelength opto-electronic device including a superlatticeMEARS TECHNOLOGIES INC·Filed 2007·Granted Feb 1, 2011·121 cites·25 claims
- 4698US7863066B2Method for making a multiple-wavelength opto-electronic device including a superlatticeMEARS TECHNOLOGIES INC·Filed 2007·Granted Jan 4, 2011·110 cites·25 claims
- 4798US7812339B2Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structuresMEARS TECHNOLOGIES INC·Filed 2008·Granted Oct 12, 2010·109 cites·23 claims
- 4898US7718996B2Semiconductor device comprising a lattice matching layerMEARS TECHNOLOGIES INC·Filed 2007·Granted May 18, 2010·110 cites·26 claims
- 4998US7700447B2Method for making a semiconductor device comprising a lattice matching layerMEARS TECHNOLOGIES INC·Filed 2007·Granted Apr 20, 2010·113 cites·28 claims
- 5098US7625767B2Methods of making spintronic devices with constrained spintronic dopantMEARS TECHNOLOGIES INC·Filed 2007·Granted Dec 1, 2009·117 cites·24 claims
Showing the top 50 of 126 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →