Inventor · disambiguated record
Bhavani Shringari Nanjundiah
Also filed as: NANJUNDIAH BHAVANI SHRINGARI
4 granted patents·47 citations·filing 2007–2008
75Inventor score
Top patents by PatentIndex Score
4 records- 0190US7647539B2System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validationIBM·Filed 2007·Granted Jan 12, 2010·29 cites·18 claims
- 0274US7584394B2System and method for pseudo-random test pattern memory allocation for processor design verification and validationIBM·Filed 2007·Granted Sep 1, 2009·7 cites·20 claims
- 0368US7689886B2System and method for predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification and validationIBM·Filed 2007·Granted Mar 30, 2010·7 cites·20 claims
- 0461US8127192B2Predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification/validation in interrupt modeARORA SAMPAN·Filed 2008·Granted Feb 28, 2012·4 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →