Inventor · disambiguated record
Sunil Suresh Hatti
Also filed as: HATTI SUNIL SURESH
15 granted patents·2 pending applications·170 citations·filing 2007–2008
93Inventor score
Top patents by PatentIndex Score
17 records- 0190US7752499B2System and method for using resource pools and instruction pools for processor design verification and validationIBM·Filed 2007·Granted Jul 6, 2010·25 cites·20 claims
- 0290US7647539B2System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validationIBM·Filed 2007·Granted Jan 12, 2010·29 cites·18 claims
- 0386US7669083B2System and method for re-shuffling test case instruction orders for processor design verification and validationIBM·Filed 2007·Granted Feb 23, 2010·22 cites·20 claims
- 0484US7992059B2System and method for testing a large memory area during processor design verification and validationIBM·Filed 2007·Granted Aug 2, 2011·15 cites·20 claims
- 0583US7747908B2System and method for creating different start cache and bus states using multiple test patterns for processor design verification and validationIBM·Filed 2007·Granted Jun 29, 2010·14 cites·20 claims
- 0682US7797650B2System and method for testing SLB and TLB cells during processor design verification and validationIBM·Filed 2007·Granted Sep 14, 2010·14 cites·20 claims
- 0778US7661023B2System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validationIBM·Filed 2007·Granted Feb 9, 2010·9 cites·20 claims
- 0874US7739570B2System and method for increasing error checking performance by calculating CRC calculations after multiple test patterns for processor design verification and validationIBM·Filed 2007·Granted Jun 15, 2010·7 cites·20 claims
- 0974US7584394B2System and method for pseudo-random test pattern memory allocation for processor design verification and validationIBM·Filed 2007·Granted Sep 1, 2009·7 cites·20 claims
- 1073US8099559B2System and method for generating fast instruction and data interrupts for processor design verification and validationCHOUDHURY SHUBHODEEP ROY·Filed 2007·Granted Jan 17, 2012·9 cites·20 claims
- 1172US7966521B2Light weight and high throughput test case generation methodology for testing cache/TLB intervention and diagnosticsIBM·Filed 2008·Granted Jun 21, 2011·5 cites·20 claims
- 1268US7689886B2System and method for predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification and validationIBM·Filed 2007·Granted Mar 30, 2010·7 cites·20 claims
- 1361US8127192B2Predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification/validation in interrupt modeARORA SAMPAN·Filed 2008·Granted Feb 28, 2012·4 cites·20 claims
- 1458US8019566B2System and method for efficiently testing cache congruence classes during processor design verification and validationIBM·Filed 2007·Granted Sep 13, 2011·1 cites·20 claims
- 1558US8006221B2System and method for testing multiple processor modes for processor design verification and validationIBM·Filed 2007·Granted Aug 23, 2011·2 cites·20 claims
- 1647US2009307468A1Generating a Test Case Micro Generator During Processor Design Verification and ValidationIBM·Filed 2008·Application pending·0 cites
- 1740US2009070570A1System and Method for Efficiently Handling InterruptsCHOUDHURY SHUBHODEEP ROY·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →