Inventor · disambiguated record
Shubhodeep Roy Choudhury
Also filed as: CHOUDHURY SHUBHODEEP ROY
10 granted patents·2 pending applications·111 citations·filing 2007–2008
89Inventor score
Technology areasG06F
Top patents by PatentIndex Score
12 records- 0190US7752499B2System and method for using resource pools and instruction pools for processor design verification and validationIBM·Filed 2007·Granted Jul 6, 2010·25 cites·20 claims
- 0286US7669083B2System and method for re-shuffling test case instruction orders for processor design verification and validationIBM·Filed 2007·Granted Feb 23, 2010·22 cites·20 claims
- 0384US7992059B2System and method for testing a large memory area during processor design verification and validationIBM·Filed 2007·Granted Aug 2, 2011·15 cites·20 claims
- 0483US7747908B2System and method for creating different start cache and bus states using multiple test patterns for processor design verification and validationIBM·Filed 2007·Granted Jun 29, 2010·14 cites·20 claims
- 0578US7661023B2System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validationIBM·Filed 2007·Granted Feb 9, 2010·9 cites·20 claims
- 0674US7739570B2System and method for increasing error checking performance by calculating CRC calculations after multiple test patterns for processor design verification and validationIBM·Filed 2007·Granted Jun 15, 2010·7 cites·20 claims
- 0774US7584394B2System and method for pseudo-random test pattern memory allocation for processor design verification and validationIBM·Filed 2007·Granted Sep 1, 2009·7 cites·20 claims
- 0873US8099559B2System and method for generating fast instruction and data interrupts for processor design verification and validationCHOUDHURY SHUBHODEEP ROY·Filed 2007·Granted Jan 17, 2012·9 cites·20 claims
- 0958US8019566B2System and method for efficiently testing cache congruence classes during processor design verification and validationIBM·Filed 2007·Granted Sep 13, 2011·1 cites·20 claims
- 1058US8006221B2System and method for testing multiple processor modes for processor design verification and validationIBM·Filed 2007·Granted Aug 23, 2011·2 cites·20 claims
- 1147US2009307468A1Generating a Test Case Micro Generator During Processor Design Verification and ValidationIBM·Filed 2008·Application pending·0 cites
- 1240US2009070570A1System and Method for Efficiently Handling InterruptsCHOUDHURY SHUBHODEEP ROY·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →