Inventor · disambiguated record
Christoph Jaeschke
Also filed as: JAESCHKE CHRISTOPH
6 granted patents·2 pending applications·26 citations·filing 2004–2011
80Inventor score
Top patents by PatentIndex Score
8 records- 0172US7996738B2Semiconductor chip with a plurality of scannable storage elements and a method for scanning storage elements on a semiconductor chipIBM·Filed 2008·Granted Aug 9, 2011·7 cites·20 claims
- 0269US7886244B2Driving values to DC adjusted/untimed nets to identify timing problemsIBM·Filed 2008·Granted Feb 8, 2011·4 cites·20 claims
- 0369US7565636B2System for performing verification of logic circuitsIBM·Filed 2008·Granted Jul 21, 2009·4 cites·3 claims
- 0466US7398494B2Method for performing verification of logic circuitsIBM·Filed 2006·Granted Jul 8, 2008·3 cites·6 claims
- 0561US7490305B2Method for driving values to DC adjusted/untimed nets to identify timing problemsIBM·Filed 2006·Granted Feb 10, 2009·2 cites·18 claims
- 0657US7213220B2Method for verification of gate level netlists using colored bitsIBM·Filed 2004·Granted May 1, 2007·6 cites·15 claims
- 0740US2012151423A1Large scale formal analysis by structural preprocessingBAUMGARTNER JASON R·Filed 2011·Application pending·0 cites
- 0831US2009228751A1method for performing logic built-in-self-test cycles on a semiconductor chip and a corresponding semiconductor chip with a test engineGLOEKLER TILMAN·Filed 2008·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →