Inventor · disambiguated record
Arthur David Kahlich
Also filed as: KAHLICH ARTHUR D · KAHLICH ARTHUR DAVID
18 granted patents·3 pending applications·47 citations·filing 1995–2019
91Inventor score
Technology areasG06F
Top patents by PatentIndex Score
21 records- 0189US9747218B2CPU security mechanisms employing thread-specific protection domainsMILL COMPUTING INC·Filed 2015·Granted Aug 29, 2017·10 cites·28 claims
- 0279US9524163B2Computer processor employing hardware-based pointer processingMILL COMPUTING INC·Filed 2014·Granted Dec 20, 2016·3 cites·23 claims
- 0378US11226821B2Computer processor employing operand data with associated meta-dataMILL COMPUTING INC·Filed 2019·Granted Jan 18, 2022·2 cites·25 claims
- 0474US10678700B2CPU security mechanisms employing thread-specific protection domainsMILL COMPUTING INC·Filed 2016·Granted Jun 9, 2020·2 cites·32 claims
- 0574US9513904B2Computer processor employing cache memory with per-byte valid bitsMILL COMPUTING INC·Filed 2014·Granted Dec 6, 2016·2 cites·28 claims
- 0673US9875106B2Computer processor employing instruction block exit predictionMILL COMPUTING INC·Filed 2014·Granted Jan 23, 2018·3 cites·27 claims
- 0772US9513921B2Computer processor employing temporal addressing for storage of transient operandsMILL COMPUTING INC·Filed 2014·Granted Dec 6, 2016·3 cites·26 claims
- 0869US9652230B2Computer processor employing dedicated hardware mechanism controlling the initialization and invalidation of cache linesMILL COMPUTING INC·Filed 2014·Granted May 16, 2017·1 cites·20 claims
- 0967US9747216B2Computer processor employing byte-addressable dedicated memory for operand storageMILL COMPUTING INC·Filed 2014·Granted Aug 29, 2017·2 cites·21 claims
- 1058US10802987B2Computer processor employing cache memory storing backless cache linesMILL COMPUTING INC·Filed 2014·Granted Oct 13, 2020·0 cites·25 claims
- 1158US9965274B2Computer processor employing bypass network using result tags for routing result operandsMILL COMPUTING INC·Filed 2014·Granted May 8, 2018·0 cites·10 claims
- 1256US9690581B2Computer processor with deferred operationsMILL COMPUTING INC·Filed 2014·Granted Jun 27, 2017·0 cites·23 claims
- 1353US2015205609A1Computer Processor Employing Operand Data With Associated Meta-DataMILL COMPUTING INC·Filed 2014·Application pending·0 cites
- 1453US2018267803A1Computer Processor Employing Phases of Operations Contained in Wide InstructionsMILL COMPUTING INC·Filed 2018·Application pending·0 cites
- 1550US9747238B2Computer processor employing split crossbar circuit for operand routing and slot-based organization of functional unitsMILL COMPUTING INC·Filed 2014·Granted Aug 29, 2017·0 cites·11 claims
- 1649US9513920B2Computer processor employing split-stream encodingMILL COMPUTING INC·Filed 2014·Granted Dec 6, 2016·0 cites·30 claims
- 1748US9785441B2Computer processor employing instructions with elided nop operationsMILL COMPUTING INC·Filed 2014·Granted Oct 10, 2017·0 cites·24 claims
- 1847US9959119B2Computer processor employing double-ended instruction decodingMILL COMPUTING INC·Filed 2014·Granted May 1, 2018·0 cites·27 claims
- 1946US2015220343A1Computer Processor Employing Phases of Operations Contained in Wide InstructionsMILL COMPUTING INC·Filed 2015·Application pending·0 cites
- 2045US5802586ACache memory having a read-modify-write operation and simultaneous burst read and write operations and a method thereforMOTOROLA INC·Filed 1995·Granted Sep 1, 1998·19 cites·16 claims
- 2139US9817669B2Computer processor employing explicit operations that support execution of software pipelined loops and a compiler that utilizes such operations for scheduling software pipelined loopsMILL COMPUTING INC·Filed 2015·Granted Nov 14, 2017·0 cites·23 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →