Inventor · disambiguated record
Pauling Chen
Also filed as: CHEN PAULING
9 granted patents·491 citations·filing 1999–2020
89Inventor score
Top patents by PatentIndex Score
9 records- 0198US6768679B1Selection circuit for accurate memory read operationsADVANCED MICRO DEVICES INC·Filed 2003·Granted Jul 27, 2004·425 cites·25 claims
- 0275US6744674B1Circuit for fast and accurate memory read operationsADVANCED MICRO DEVICES INC·Filed 2003·Granted Jun 1, 2004·14 cites·20 claims
- 0365US6788583B2Pre-charge method for reading a non-volatile memory cellADVANCED MICRO DEVICES INC·Filed 2002·Granted Sep 7, 2004·14 cites·19 claims
- 0463US6885250B1Cascode amplifier circuit for generating and maintaining a fast, stable and accurate bit line voltageADVANCED MICRO DEVICES INC·Filed 2004·Granted Apr 26, 2005·10 cites·8 claims
- 0557US6771545B1Method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell arrayADVANCED MICRO DEVICES INC·Filed 2003·Granted Aug 3, 2004·10 cites·18 claims
- 0650US6240017B1Reduction of voltage stress across a gate oxide and across a junction within a high voltage transistor of an erasable memory deviceADVANCED MICRO DEVICES INC·Filed 1999·Granted May 29, 2001·11 cites·7 claims
- 0747US6768677B2Cascode amplifier circuit for producing a fast, stable and accurate bit line voltageADVANCED MICRO DEVICES INC·Filed 2002·Granted Jul 27, 2004·4 cites·12 claims
- 0845US11119854B2Method of controlling verification operations for error correction of non-volatile memory device, and non-volatile memory deviceELITE SEMICONDUCTOR MEMORY TECH INC·Filed 2020·Granted Sep 14, 2021·0 cites·11 claims
- 0942US6275424B1Reduction of voltage stress across a gate oxide and across a junction within a high voltage transistor of an erasable memory deviceADVANCED MICRO DEVICES INC·Filed 2001·Granted Aug 14, 2001·3 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →