Inventor · disambiguated record
Raymond L. Strouble
Also filed as: STROUBLE RAYMOND · STROUBLE RAYMOND L
12 granted patents·1,204 citations·filing 1990–2000
95Inventor score
Top patents by PatentIndex Score
12 records- 0197US6425107B1Data encoder/decoder for a high speed serial linkFUJITSU NETWORK COMMUNICATIONS·Filed 2000·Granted Jul 23, 2002·119 cites·16 claims
- 0295US5872769ALinked list structures for multiple levels of control in an ATM switchFUJITSU NETWORK COMMUNICATIONS·Filed 1996·Granted Feb 16, 1999·185 cites·17 claims
- 0393US5982771AControlling bandwidth allocation using a pace counterFUJITSU NETWORK COMMUNICATIONS·Filed 1996·Granted Nov 9, 1999·130 cites·36 claims
- 0491US5347648AEnsuring write ordering under writeback cache error conditionsDIGITAL EQUIPMENT CORP·Filed 1992·Granted Sep 13, 1994·188 cites·20 claims
- 0589US5317720AProcessor system with writeback cache using writeback and non writeback transactions stored in separate queuesDIGITAL EQUIPMENT CORP·Filed 1993·Granted May 31, 1994·168 cites·30 claims
- 0687US5996019ANetwork link access scheduling using a plurality of prioritized lists containing queue identifiersFUJITSU NETWORK COMMUNICATIONS·Filed 1996·Granted Nov 30, 1999·83 cites·20 claims
- 0786US6256674B1Method and apparatus for providing buffer state flow control at the link level in addition to flow control on a per-connection basisFUJITSU NETWORK COMMUNICATIONS·Filed 1999·Granted Jul 3, 2001·63 cites·29 claims
- 0886US5155843AError transition mode for multi-processor systemDIGITAL EQUIPMENT CORP·Filed 1990·Granted Oct 13, 1992·143 cites·15 claims
- 0975US5896511AMethod and apparatus for providing buffer state flow control at the link level in addition to flow control on a per-connection basisFUJITSU NETWORK COMMUNICATIONS·Filed 1996·Granted Apr 20, 1999·34 cites·9 claims
- 1073US6195764B1Data encoder/decoder for a high speed serial linkFUJITSU NETWORK COMMUNICATIONS·Filed 1998·Granted Feb 27, 2001·32 cites·8 claims
- 1170US5781533ALink buffer sharing method and apparatusFUJITSU NETWORK COMMUNICATIONS·Filed 1997·Granted Jul 14, 1998·26 cites·82 claims
- 1263US6049901ATest system for integrated circuits using a single memory for both the parallel and scan modes of testingFiled 1997·Granted Apr 11, 2000·33 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →