Inventor · disambiguated record
Asit K. Mallick
Also filed as: MALLICK ASIT · MALLICK ASIT K
36 granted patents·14 pending applications·127 citations·filing 2000–2023
96Inventor score
Top patents by PatentIndex Score
50 records- 0193US10048881B2Restricted address translation to protect against device-TLB vulnerabilitiesINTEL CORP·Filed 2016·Granted Aug 14, 2018·10 cites·23 claims
- 0287US12253958B2System for address mapping and translation protectionINTEL CORP·Filed 2021·Granted Mar 18, 2025·1 cites·25 claims
- 0387US10263988B2Protected container key management processors, methods, systems, and instructionsINTEL CORP·Filed 2016·Granted Apr 16, 2019·6 cites·25 claims
- 0487US9747123B2Technologies for multi-level virtualizationINTEL CORP·Filed 2015·Granted Aug 29, 2017·6 cites·24 claims
- 0587US7768518B2Enabling multiple instruction stream/multiple data stream extensions on microprocessorsINTEL CORP·Filed 2006·Granted Aug 3, 2010·19 cites·15 claims
- 0685US10515023B2System for address mapping and translation protectionSAHITA RAVI L·Filed 2016·Granted Dec 24, 2019·3 cites·21 claims
- 0784US11436161B2System for address mapping and translation protectionINTEL CORP·Filed 2019·Granted Sep 6, 2022·2 cites·20 claims
- 0884US7383374B2Method and apparatus for managing virtual addressesINTEL CORP·Filed 2005·Granted Jun 3, 2008·14 cites·28 claims
- 0981US10503664B2Virtual machine manager for address mapping and translation protectionINTEL CORP·Filed 2016·Granted Dec 10, 2019·2 cites·19 claims
- 1079US9916257B2Method and apparatus for TLB shoot-down in a heterogeneous computing system supporting shared virtual memorySANKARAN RAJESH M·Filed 2011·Granted Mar 13, 2018·6 cites·20 claims
- 1179US9164764B2Single instruction for specifying and saving a subset of registers, specifying a pointer to a work-monitoring function to be executed after waking, and entering a low-power modeINTEL CORP·Filed 2014·Granted Oct 20, 2015·3 cites·20 claims
- 1279US8635415B2Managing and implementing metadata in central processing unit using register extensionsPATEL BAIJU V·Filed 2009·Granted Jan 21, 2014·11 cites·13 claims
- 1378US9239801B2Systems and methods for preventing unauthorized stack pivotingINTEL CORP·Filed 2013·Granted Jan 19, 2016·5 cites·19 claims
- 1478US8762692B2Single instruction for specifying and saving a subset of registers, specifying a pointer to a work-monitoring function to be executed after waking, and entering a low-power modeSCHUCHMAN ETHAN·Filed 2007·Granted Jun 24, 2014·9 cites·31 claims
- 1575US6745346B2Method for efficiently identifying errant processes in a computer system by the operating system (OS) for error containment and error recoveryINTEL CORP·Filed 2000·Granted Jun 1, 2004·18 cites·28 claims
- 1670US11683310B2Protecting supervisor mode informationINTEL CORP·Filed 2021·Granted Jun 20, 2023·0 cites·30 claims
- 1769US10999284B2Protecting supervisor mode informationINTEL CORP·Filed 2020·Granted May 4, 2021·0 cites·30 claims
- 1868US12430162B2User-level interprocessor interruptsINTEL CORP·Filed 2021·Granted Sep 30, 2025·0 cites·18 claims
- 1965US9069605B2Mechanism to schedule threads on OS-sequestered sequencers without operating system interventionINTEL CORP·Filed 2013·Granted Jun 30, 2015·1 cites·20 claims
- 2064US12020031B2Methods, apparatus, and instructions for user-level thread suspensionINTEL CORP·Filed 2021·Granted Jun 25, 2024·0 cites·18 claims
- 2164US11019061B2Protecting supervisor mode informationINTEL CORP·Filed 2018·Granted May 25, 2021·0 cites·20 claims
- 2262US7131029B2Method for efficiently identifying errant processes in a computer system by the operating system (OS) for error containment and error recoveryINTEL CORP·Filed 2004·Granted Oct 31, 2006·7 cites·29 claims
- 2359US10135825B2Protecting supervisor mode informationINTEL CORP·Filed 2014·Granted Nov 20, 2018·0 cites·12 claims
- 2456US12340224B2Systems, methods, and apparatuses to control CPU speculation for the prevention of side-channel attacksINTEL CORP·Filed 2023·Granted Jun 24, 2025·0 cites·7 claims
- 2556US9600283B2Single instruction for specifying a subset of registers to save prior to entering low-power mode, and for specifying a pointer to a function executed after exiting low-power modeINTEL CORP·Filed 2015·Granted Mar 21, 2017·0 cites·19 claims
- 2654US11675594B2Systems, methods, and apparatuses to control CPU speculation for the prevention of side-channel attacksINTEL CORP·Filed 2018·Granted Jun 13, 2023·0 cites·18 claims
- 2754US11630687B2Compacted context state managementTAHOE RES LTD·Filed 2018·Granted Apr 18, 2023·0 cites·15 claims
- 2854US9323533B2Supervisor mode execution protectionVEN ADRIAAN VAN DE·Filed 2011·Granted Apr 26, 2016·1 cites·17 claims
- 2953US9898330B2Compacted context state managementINTEL CORP·Filed 2013·Granted Feb 20, 2018·0 cites·20 claims
- 3053US8607235B2Mechanism to schedule threads on OS-sequestered sequencers without operating system interventionHANKINS RICHARD A·Filed 2004·Granted Dec 10, 2013·3 cites·34 claims
- 3152US11023233B2Methods, apparatus, and instructions for user level thread suspensionINTEL CORP·Filed 2016·Granted Jun 1, 2021·0 cites·15 claims
- 3251US10120805B2Managing memory for secure enclavesINTEL CORP·Filed 2017·Granted Nov 6, 2018·0 cites·17 claims
- 3350US11354213B2Utilization metrics for processing enginesINTEL CORP·Filed 2018·Granted Jun 7, 2022·0 cites·20 claims
- 3450US9977743B2Managing enclave memory pagesINTEL CORP·Filed 2016·Granted May 22, 2018·0 cites·25 claims
- 3549US10324862B2Supporting oversubscription of guest enclave memory pagesINTEL CORP·Filed 2016·Granted Jun 18, 2019·0 cites·20 claims
- 3648US2024338238A1Host to guest notificationINTEL CORP·Filed 2022·Application pending·0 cites
- 3748US2019102274A1Utilization Metrics for Processing EnginesINTEL CORP·Filed 2017·Application pending·0 cites
- 3846US2024192981A1Exitless guest to host notificationINTEL CORP·Filed 2021·Application pending·0 cites
- 3945US2022206819A1Dynamic detection of speculation vulnerabilitiesINTEL CORP·Filed 2020·Application pending·0 cites
- 4045US2022207149A1Data tainting to mitigate speculation vulnerabilitiesINTEL CORP·Filed 2020·Application pending·0 cites
- 4143US2007136724A1Transferring registers in transitions between computer environmentsSHARMA ARUN·Filed 2005·Application pending·0 cites
- 4242US2019205061A1Processor, method, and system for reducing latency in accessing remote registersINTEL CORP·Filed 2017·Application pending·0 cites
- 4341US2022206818A1Hardening execution hardware against speculation vulnerabilitiesINTEL CORP·Filed 2020·Application pending·0 cites
- 4441US2022207154A1Dynamic mitigation of speculation vulnerabilitiesINTEL CORP·Filed 2020·Application pending·0 cites
- 4541US2022207138A1Hardening store hardware against speculation vulnerabilitiesINTEL CORP·Filed 2020·Application pending·0 cites
- 4641US2022207146A1Hardening load hardware against speculation vulnerabilitiesINTEL CORP·Filed 2020·Application pending·0 cites
- 4741US2022207148A1Hardening branch hardware against speculation vulnerabilitiesINTEL CORP·Filed 2020·Application pending·0 cites
- 4841US2022207147A1Hardening registers against speculation vulnerabilitiesINTEL CORP·Filed 2020·Application pending·0 cites
- 4939US2018006809A1Data security in a cloud networkINTEL CORP·Filed 2016·Application pending·0 cites
- 5036US9785463B2Using per task time slice information to improve dynamic performance state selectionVAN DE VEN ADRIAAN·Filed 2010·Granted Oct 10, 2017·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →